Biggs; Julie C.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Biggs; Julie C..The latest application filed is for "forming robust solder interconnect structures by reducing effects of seed layer underetching".

Company Profile

0.5.5

Biggs; Julie C. - Wappingers Falls NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Forming robust solder interconnect structures by reducing effects of seed layer underetching Grant 7,767,575 - Srivastava , et al. August 3, 2	2010-08-03
Method of forming a bond pad on an I/C chip and resulting structure Grant 7,572,726 - Biggs , et al. August 11, 2	2009-08-11
Forming Robust Solder Interconnect Structures By Reducing Effects Of Seed Layer Underetching App 20090163019 - Srivastava; Kamalesh K. ; et al.	2009-06-25
Method for forming robust solder interconnect structures by reducing effects of seed layer underetching Grant 7,473,997 - Srivastava , et al. January 6, 2	2009-01-06
Method of forming a bond pad on an I/C chip and resulting structure App 20060081981 - Biggs; Julie C. ; et al.	2006-04-20
Method for forming robust solder interconnect structures by reducing effects of seed layer underetching Grant 6,995,084 - Srivastava , et al. February 7, 2	2006-02-07
I/C chip suitable for wire bonding Grant 6,995,475 - Biggs , et al. February 7, 2	2006-02-07
Method For Forming Robust Solder Interconnect Structures By Reducing Effects Of Seed Layer Underetching App 20060009022 - Srivastava; Kamalesh K. ; et al.	2006-01-12
Method For Forming Robust Solder Interconnect Structures By Reducing Effects Of Seed Layer Underetching App 20050208748 - Srivastava, Kamalesh K. ; et al.	2005-09-22
Method of forming a bond pad on an I/C chip and resulting structure App 20050062170 - Biggs, Julie C. ; et al.	2005-03-24

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