Bickford; Jeanne P.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Bickford; Jeanne P..The latest application filed is for "slew window shift placement method to reduce hot spots and recover vt/area".

Company Profile

3.83.74

Bickford; Jeanne P. - Essex Junction VT
Bickford; Jeanne P. - Essex Juntion VT
Bickford; Jeanne P. - Exxex Junction VT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Integrated circuit chip reliability qualification using a sample-specific expected fail rate Grant 10,539,611 - Bickford , et al. Ja	2020-01-21
Pre-test power-optimized bin reassignment following selective voltage binning Grant 10,295,592 - Arsovski , et al.	2019-05-21
Performance matching in three-dimensional (3D) integrated circuit (IC) using back-bias compensation Grant 10,013,519 - Mandal , et al. July 3, 2	2018-07-03
Burn-in power performance optimization Grant 9,940,430 - Bickford , et al. April 10, 2	2018-04-10
Slew Window Shift Placement Method To Reduce Hot Spots And Recover Vt/area App 20180089354 - Chandra; Alok ; et al.	2018-03-29
Performance Matching In Three-dimensional (3d) Integrated Circuit (ic) Using Back-bias Compensation App 20180082007 - Mandal; Sudeep ; et al.	2018-03-22
Integrated Circuit Chip Reliability Qualification Using A Sample-specific Expected Fail Rate App 20180052201 - Bickford; Jeanne P. ; et al.	2018-02-22
Integrated circuit chip reliability qualification using a sample-specific expected fail rate Grant 9,891,275 - Bickford , et al. February 13, 2	2018-02-13
Timing/power risk optimized selective voltage binning using non-linear voltage slope Grant 9,865,486 - Arsovski , et al. January 9, 2	2018-01-09
Area and/or power optimization through post-layout modification of integrated circuit (IC) design blocks Grant 9,852,259 - Bickford , et al. December 26, 2	2017-12-26
On-chip usable life depletion meter and associated method Grant 9,791,502 - Bickford , et al. October 17, 2	2017-10-17
Timing/power Risk Optimized Selective Voltage Binning Using Non-linear Voltage Slope App 20170287756 - ARSOVSKI; IGOR ; et al.	2017-10-05
Pre-test Power-optimized Bin Reassignment Following Selective Voltage Binning App 20170276726 - Arsovski; Igor ; et al.	2017-09-28
Selective voltage binning leakage screen Grant 9,772,374 - Bickford , et al. September 26, 2	2017-09-26
Temperature-aware integrated circuit design methods and systems Grant 9,767,240 - Bickford , et al. September 19, 2	2017-09-19
Pre-test power-optimized bin reassignment following selective voltage binning Grant 9,759,767 - Arsovski , et al. September 12, 2	2017-09-12
Electromigration-aware integrated circuit design methods and systems Grant 9,740,815 - Bickford , et al. August 22, 2	2017-08-22
Resistance Measurement-dependent Integrated Circuit Chip Reliability Estimation App 20170212165 - Bickford; Jeanne P. ; et al.	2017-07-27
Area And/or Power Optimization Through Post-layout Modification Of Integrated Circuit (ic) Design Blocks App 20170212977 - Bickford; Jeanne P. ; et al.	2017-07-27
Burn-in Power Performance Optimization App 20170161426 - Bickford; Jeanne P. ; et al.	2017-06-08
Temperature-aware Integrated Circuit Design Methods And Systems App 20170147727 - Bickford; Jeanne P. ; et al.	2017-05-25
Threshold voltage (VT)-type transistor sensitive and/or fan-out sensitive selective voltage binning Grant 9,653,330 - Bickford , et al. May 16, 2	2017-05-16
Integrated circuit chip reliability using reliability-optimized failure mechanism targeting Grant 9,639,645 - Bickford , et al. May 2, 2	2017-05-02
Electromigration-aware Integrated Circuit Design Methods And Systems App 20170116367 - Bickford; Jeanne P. ; et al.	2017-04-27
System and method for identifying operating temperatures and modifying of integrated circuits Grant 9,625,325 - Bickford , et al. April 18, 2	2017-04-18
Integrated circuit chip design methods and systems using process window-aware timing analysis Grant 9,619,609 - Bickford , et al. April 11, 2	2017-04-11
Integrated Circuit Chip Design Methods And Systems Using Process Window-aware Timing Analysis App 20170083661 - Bickford; Jeanne P. ; et al.	2017-03-23
Method and system for timing violations in a circuit Grant 9,569,571 - Bickford , et al. February 14, 2	2017-02-14
Method and structure for multi-core chip product test and selective voltage binning disposition Grant 9,557,378 - Bickford , et al. January 31, 2	2017-01-31
Systems and methods for controlling integrated circuit chip temperature using timing closure-based adaptive frequency scaling Grant 9,552,447 - Bickford , et al. January 24, 2	2017-01-24
Multiple manufacturing line qualification Grant 9,536,796 - Bickford , et al. January 3, 2	2017-01-03
Integrated Circuit Chip Reliability Qualification Using A Sample-specific Expected Fail Rate App 20160377674 - Bickford; Jeanne P. ; et al.	2016-12-29
Integrated Circuit Chip Reliability Using Reliability-optimized Failure Mechanism Targeting App 20160371413 - Bickford; Jeanne P. ; et al.	2016-12-22
Systems and methods for semiconductor line scribe line centering Grant 9,514,999 - Bickford , et al. December 6, 2	2016-12-06
Reliability-optimized selective voltage binning Grant 9,489,482 - Bickford , et al. November 8, 2	2016-11-08
On-chip Usable Life Depletion Meter And Associated Method App 20160320214 - Bickford; Jeanne P. ; et al.	2016-11-03
Systems And Methods For Controlling Integrated Circuit Chip Temperature Using Timing Closure-based Adaptive Frequency Scaling App 20160314229 - Bickford; Jeanne P. ; et al.	2016-10-27
Pre-test Power-optimized Bin Reassignment Following Selective Voltage Binning App 20160313394 - Arsovski; Igor ; et al.	2016-10-27
Reliability test screen optimization Grant 9,429,619 - Anemikos , et al. August 30, 2	2016-08-30
System And Method For Identifying Operating Temperatures And Modifying Of Integrated Circuits App 20160240479 - Bickford; Jeanne P. ; et al.	2016-08-18
Systems And Methods To Prevent Incorporation Of A Used Integrated Circuit Chip Into A Product App 20160238653 - Bickford; Jeanne P. ; et al.	2016-08-18
System integrator and system integration method with reliability optimized integrated circuit chip selection Grant 9,354,953 - Bickford , et al. May 31, 2	2016-05-31
System and method for managing circuit performance and power consumption by selectively adjusting supply voltage over time Grant 9,269,407 - Bickford , et al. February 23, 2	2016-02-23
Balancing sensitivities with respect to timing closure for integrated circuits Grant 9,262,569 - Bickford , et al. February 16, 2	2016-02-16
System Integrator And System Integration Method With Reliability Optimized Integrated Circuit Chip Selection App 20160026517 - Bickford; Jeanne P. ; et al.	2016-01-28
Updating Reliability Predictions Using Manufacturing Assessment Data App 20160019328 - Bickford; Jeanne P. ; et al.	2016-01-21
Limiting skew between different device types to meet performance requirements of an integrated circuit Grant 9,171,125 - Arsovski , et al. October 27, 2	2015-10-27
Adaptive power control using timing canonicals Grant 9,157,956 - Bickford , et al. October 13, 2	2015-10-13
Systems and methods for system power estimation Grant 9,152,168 - Bickford , et al. October 6, 2	2015-10-06
Limiting Skew Between Different Device Types To Meet Performance Requirements Of An Integrated Circuit App 20150242560 - ARSOVSKI; Igor ; et al.	2015-08-27
Balancing Sensitivities With Respect To Timing Closure For Integrated Circuits App 20150234969 - BICKFORD; Jeanne P. ; et al.	2015-08-20
Systems and methods for single cell product path delay analysis Grant 9,104,834 - Bickford , et al. August 11, 2	2015-08-11
Semiconductor device reliability model and methodologies for use thereof Grant 9,064,087 - Bickford , et al. June 23, 2	2015-06-23
Integrated circuit product yield optimization using the results of performance path testing Grant 9,058,034 - Bickford , et al. June 16, 2	2015-06-16
Semiconductor Device Reliability Model And Methodologies For Use Thereof App 20150106780 - BICKFORD; Jeanne P. ; et al.	2015-04-16
Semiconductor timing improvement Grant 8,966,431 - Bickford , et al. February 24, 2	2015-02-24
Reliability evaluation and system fail warning methods using on chip parametric monitors Grant 8,949,767 - Bickford , et al. February 3, 2	2015-02-03
Systems And Methods For Single Cell Product Path Delay Analysis App 20150033199 - BICKFORD; Jeanne P. ; et al.	2015-01-29
Semiconductor device reliability model and methodologies for use thereof Grant 8,943,444 - Bickford , et al. January 27, 2	2015-01-27
Semiconductor Device Reliability Model And Methodologies For Use Thereof App 20140380261 - BICKFORD; Jeanne P. ; et al.	2014-12-25
Systems and methods for single cell product path delay analysis Grant 8,904,329 - Bickford , et al. December 2, 2	2014-12-02
Selective voltage binning within a three-dimensional integrated chip stack Grant 8,850,380 - Bickford , et al. September 30, 2	2014-09-30
Power and timing optimization for an integrated circuit by voltage modification across various ranges of temperatures Grant 8,843,874 - Bickford , et al. September 23, 2	2014-09-23
Power/performance optimization through temperature/voltage control Grant 8,839,170 - Bickford , et al. September 16, 2	2014-09-16
Power/performance optimization through continuously variable temperature-based voltage control Grant 8,839,165 - Bickford , et al. September 16, 2	2014-09-16
Method and system allowing for semiconductor design rule optimization Grant 8,839,177 - Aubel , et al. September 16, 2	2014-09-16
Selective Voltage Binning Within A Three-dimensional Integrated Chip Stack App 20140229909 - Bickford; Jeanne P. ; et al.	2014-08-14
Power/performance Optimization Through Continuously Variable Temperature-based Voltage Control App 20140215429 - Bickford; Jeanne P. ; et al.	2014-07-31
Systems And Methods For Single Cell Product Path Delay Analysis App 20140195995 - Bickford; Jeanne P. ; et al.	2014-07-10
Systems And Methods For Semiconductor Line Scribe Centering App 20140188265 - BICKFORD; Jeanne P. ; et al.	2014-07-03
Multiple Manufacturing Line Qualification App 20140188266 - BICKFORD; Jeanne P. ; et al.	2014-07-03
Semiconductor Timing Improvement App 20140143748 - BICKFORD; Jeanne P. ; et al.	2014-05-22
Method and system to predict a number of electromigration critical elements Grant 8,726,201 - Bickford , et al. May 13, 2	2014-05-13
Frequency selection with selective voltage binning Grant 8,719,763 - Bickford , et al. May 6, 2	2014-05-06
Selective Voltage Binning Leakage Screen App 20140100799 - BICKFORD; Jeanne P. ; et al.	2014-04-10
Adaptive Power Control Using Timing Canonicals App 20140074422 - Bickford; Jeanne P. ; et al.	2014-03-13
Product Reliability Estimation App 20140067302 - BICKFORD; Jeanne P. ; et al.	2014-03-06
Systems And Methods For System Power Estimation App 20140068283 - BICKFORD; Jeanne P. ; et al.	2014-03-06
Integrated Circuit Product Yield Optimization Using The Results Of Performance Path Testing App 20140046466 - Bickford; Jeanne P. ; et al.	2014-02-13
Reliability Test Screen Optimization App 20140039664 - ANEMIKOS; THEODOROS E. ; et al.	2014-02-06
Method And Structure For Multi-core Chip Product Test And Selective Voltage Binning Disposition App 20140024145 - BICKFORD; JEANNE P. ; et al.	2014-01-23
Power/performance Optimization Through Temperature/voltage Control App 20130326459 - Bickford; Jeanne P. ; et al.	2013-12-05
Reliability Evaluation And System Fail Warning Methods Using On Chip Parametric Monitors App 20130326442 - Bickford; Jeanne P. ; et al.	2013-12-05
Power And Timing Optimization For An Integrated Circuit By Voltage Modification Across Various Ranges Of Temperatures App 20130326460 - Bickford; Jeanne P. ; et al.	2013-12-05
Circuit design with growable capacitor arrays Grant 8,578,314 - Bickford , et al. November 5, 2	2013-11-05
Power and timing optimization for an integrated circuit by voltage modification across various ranges of temperatures Grant 8,543,960 - Bickford , et al. September 24, 2	2013-09-24
Test path selection and test program generation for performance testing integrated circuit chips Grant 8,543,966 - Bickford , et al. September 24, 2	2013-09-24
System yield optimization using the results of integrated circuit chip performance path testing Grant 8,539,429 - Bickford , et al. September 17, 2	2013-09-17
Reliability evaluation and system fail warning methods using on chip parametric monitors Grant 8,504,975 - Bickford , et al. August 6, 2	2013-08-06
Disposition of integrated circuits using performance sort ring oscillator and performance path testing Grant 8,490,040 - Bickford , et al. July 16, 2	2013-07-16
Disposition Of Integrated Circuits Using Performance Sort Ring Oscillator And Performance Path Testing App 20130125076 - Bickford; Jeanne P. ; et al.	2013-05-16
Test Path Selection And Test Program Generation For Performance Testing Integrated Circuit Chips App 20130125073 - Bickford; Jeanne P. ; et al.	2013-05-16
Speed Binning For Dynamic And Adaptive Power Control App 20130113514 - Anemikos; Theodoros E. ; et al.	2013-05-09
Methods and systems to meet technology pattern density requirements of semiconductor fabrication processes Grant 8,423,945 - Bickford , et al. April 16, 2	2013-04-16
Speed binning for dynamic and adaptive power control Grant 8,421,495 - Anemikos , et al. April 16, 2	2013-04-16
Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool Grant 8,418,090 - Bickford , et al. April 9, 2	2013-04-09
Method and system to optimize semiconductor products for power, performance, noise, and cost through use of variable power supply voltage compression Grant 8,302,063 - Bickford , et al. October 30, 2	2012-10-30
Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same Grant 8,234,594 - Anderson , et al. July 31, 2	2012-07-31
Method For Computing The Sensitivity Of A Vlsi Design To Both Random And Systematic Defects Using A Critical Area Analysis Tool App 20120137262 - Bickford; Jeanne P. ; et al.	2012-05-31
Reliability Evaluation And System Fail Warning Methods Using On Chip Parametric Monitors App 20120105240 - Bickford; Jeanne P. ; et al.	2012-05-03
Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool Grant 8,132,129 - Bickford , et al. March 6, 2	2012-03-06
Reliability evaluation and system fail warning methods using on chip parametric monitors Grant 8,095,907 - Bickford , et al. January 10, 2	2012-01-10
Method And System To Optimize Semiconductor Products For Power, Performance, Noise, And Cost Through Use Of Variable Power Supply Voltage Compression App 20110288829 - BICKFORD; Jeanne P. ; et al.	2011-11-24
Methods and Systems to Meet Technology Pattern Density Requirements of Semiconductor Fabrication Processes App 20110289470 - BICKFORD; Jeanne P. ; et al.	2011-11-24
Method And System To Predict A Number Of Electromigration Critical Elements App 20110283249 - BICKFORD; Jeanne P. ; et al.	2011-11-17
Computer readable medium, system and associated method for designing integrated circuits with loop insertions Grant 7,996,808 - Arp , et al. August 9, 2	2011-08-09
Design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same Grant 7,984,394 - Anderson , et al. July 19, 2	2011-07-19
Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same Grant 7,960,836 - Anderson , et al. June 14, 2	2011-06-14
Across reticle variation modeling and related reticle Grant 7,803,644 - Balch , et al. September 28, 2	2010-09-28
Design Structure for a Redundant Micro-Loop Structure for use in an Integrated Circuit Physical Design Process and Method of Forming the Same App 20100211923 - Anderson; Brent A. ; et al.	2010-08-19
Testing method using a scalable parametric measurement macro Grant 7,656,182 - Bickford , et al. February 2, 2	2010-02-02
Design Structure for a Redundant Micro-Loop Structure for use in an Integrated Circuit Physical Design Process and Method of Forming the Same App 20090158231 - Anderson; Brent A. ; et al.	2009-06-18
Method For Computing The Sensistivity Of A Vlsi Design To Both Random And Systematic Defects Using A Critical Area Analysis Tool App 20090113360 - BICKFORD; JEANNE P. ; et al.	2009-04-30
Equivalent Gate Count Yield Estimation For Integrated Circuit Devices App 20090112352 - Barnett; Thomas S. ; et al.	2009-04-30
Reliability Evaluation And System Fail Warning Methods Using On Chip Parametric Monitors App 20090106712 - Bickford; Jeanne P. ; et al.	2009-04-23
Across Reticle Variation Modeling And Related Reticle App 20090068772 - Balch; Bruce W. ; et al.	2009-03-12
Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool Grant 7,487,476 - Bickford , et al. February 3, 2	2009-02-03
Computer Readable Medium, System and Associated Method For Designing Integrated Circuits With Loop Insertions App 20090031274 - Arp; Andreas ; et al.	2009-01-29
Equivalent gate count yield estimation for integrated circuit devices Grant 7,477,961 - Barnett , et al. January 13, 2	2009-01-13
Testing Method Using A Scalable Parametric Measurement Macro App 20080231307 - Bickford; Jeanne P. ; et al.	2008-09-25
Yield optimization in router for systematic defects Grant 7,398,485 - Bickford , et al. July 8, 2	2008-07-08
Redundant Micro-loop Structure For Use In An Intergrated Circuit Physical Design Process And Method Of Forming The Same App 20080150149 - Anderson; Brent A. ; et al.	2008-06-26
Method of facilitating integrated circuit design using manufactured property values Grant 7,380,233 - Bickford , et al. May 27, 2	2008-05-27
Redundant Micro-Loop Structure For Use In An Integrated Circuit Physical Design Process And Method Of Forming The Same App 20080097738 - Anderson; Brent A. ; et al.	2008-04-24
Method For Improved Equivalent Gate Count Yield Estimation For Integrated Circuit Devices App 20070265722 - Barnett; Thomas S. ; et al.	2007-11-15
Method For Computing The Sensitivity Of A Vlsi Design To Both Random And Systematic Defects Using A Critical Area Analysis Tool App 20070240085 - Bickford; Jeanne P. ; et al.	2007-10-11
Method Of Facilitating Integrated Circuit Design App 20070050736 - Bickford; Jeanne P. ; et al.	2007-03-01
Method and system for providing quality control on wafers running on a manufacturing line Grant 7,089,132 - Bickford , et al. August 8, 2	2006-08-08
Method for modeling integrated circuit yield Grant 7,013,441 - Bickford , et al. March 14, 2	2006-03-14
Method And System For Providing Quality Control On Wafers Running On A Manufacturing Line App 20050267705 - Bickford, Jeanne P. ; et al.	2005-12-01
Method For Modeling Integrated Circuit Yield App 20050071788 - Bickford, Jeanne P. ; et al.	2005-03-31