Bian; Zailong
Patent Applications and Registrations
Patent applications and USPTO patent grants for Bian; Zailong.The latest application filed is for "semiconductor constructions, memory arrays, electronic systems, and methods of forming semiconductor constructions".
- Bian; Zailong - Boise ID
- Bian; Zailong - Manassas VA US
| Patent | Date |
|---|---|
| Semiconductor Constructions, Memory Arrays, Electronic Systems, and Methods of Forming Semiconductor Constructions App 20220028865 - Bian; Zailong ; et al. | 2022-01-27 |
| Semiconductor constructions, memory arrays, electronic systems, and methods of forming semiconductor constructions Grant 11,171,205 - Bian , et al. November 9, 2 | 2021-11-09 |
| Semiconductor Constructions, Memory Arrays, Electronic Systems, and Methods of Forming Semiconductor Constructions App 20200212175 - Bian; Zailong ; et al. | 2020-07-02 |
| Electronic systems and methods of forming semiconductor constructions Grant 10,622,442 - Bian , et al. | 2020-04-14 |
| Capping poly channel pillars in stacked circuits Grant 10,319,678 - Li , et al. | 2019-06-11 |
| Electronic Systems and Methods of Forming Semiconductor Constructions App 20190096994 - Bian; Zailong ; et al. | 2019-03-28 |
| Memory arrays Grant 10,170,545 - Bian , et al. J | 2019-01-01 |
| Conductive structures, wordlines and transistors Grant 10,147,727 - Goswami , et al. De | 2018-12-04 |
| Memory Arrays App 20180175145 - Bian; Zailong ; et al. | 2018-06-21 |
| Conductive Structures, Wordlines and Transistors App 20180175039 - Goswami; Jaydeb ; et al. | 2018-06-21 |
| Conductive Structures, Wordlines And Transistors App 20180138182 - Goswami; Jaydeb ; et al. | 2018-05-17 |
| Conductive structures, wordlines and transistors Grant 9,972,628 - Goswami , et al. May 15, 2 | 2018-05-15 |
| Memory arrays Grant 9,929,233 - Bian , et al. March 27, 2 | 2018-03-27 |
| Integrated circuitry Grant 9,754,879 - Bian September 5, 2 | 2017-09-05 |
| Method For Forming A Metal Cap In A Semiconductor Memory Device App 20170133585 - Balakrishnan; Muralikrishnan ; et al. | 2017-05-11 |
| Memory Arrays App 20170104059 - Bian; Zailong ; et al. | 2017-04-13 |
| Method for forming a metal cap in a semiconductor memory device Grant 9,577,192 - Balakrishnan , et al. February 21, 2 | 2017-02-21 |
| Memory arrays Grant 9,559,163 - Bian , et al. January 31, 2 | 2017-01-31 |
| Capping Poly Channel Pillars In Stacked Circuits App 20160247756 - Li; Hongqi ; et al. | 2016-08-25 |
| Confined resistance variable memory cells and methods Grant 9,362,495 - Bian June 7, 2 | 2016-06-07 |
| Methods of Fabricating Integrated Circuitry App 20160126181 - Bian; Zailong | 2016-05-05 |
| Capping poly channel pillars in stacked circuits Grant 9,263,459 - Li , et al. February 16, 2 | 2016-02-16 |
| Method For Forming A Metal Cap In A Semiconductor Memory Device App 20150340247 - Balakrishnan; Muralikrishnan ; et al. | 2015-11-26 |
| Memory Arrays App 20140374833 - Bian; Zailong ; et al. | 2014-12-25 |
| Memory arrays Grant 8,829,643 - Bian , et al. September 9, 2 | 2014-09-09 |
| Methods Of Fabricating Integrated Circuitry App 20140248767 - Bian; Zailong | 2014-09-04 |
| Confined Resistance Variable Memory Cells And Methods App 20140151629 - Bian; Zailong | 2014-06-05 |
| Confined resistance variable memory cells and methods Grant 8,597,974 - Bian December 3, 2 | 2013-12-03 |
| Isolation regions Grant 8,546,888 - Bian , et al. October 1, 2 | 2013-10-01 |
| Confined Resistance Variable Memory Cells And Methods App 20120019349 - Bian; Zailong | 2012-01-26 |
| Methods of forming copper-comprising conductive lines in the fabrication of integrated circuitry Grant 8,084,355 - Bian December 27, 2 | 2011-12-27 |
| Isolation Regions App 20110241096 - Bian; Zailong ; et al. | 2011-10-06 |
| Isolation regions Grant 7,968,425 - Bian , et al. June 28, 2 | 2011-06-28 |
| Memory Arrays App 20100276780 - Bian; Zailong ; et al. | 2010-11-04 |
| Methods Of Forming Copper-Comprising Conductive Lines In The Fabrication Of Integrated Circuitry App 20100248472 - Bian; Zailong | 2010-09-30 |
| Semiconductor constructions Grant 7,772,672 - Bian , et al. August 10, 2 | 2010-08-10 |
| Methods of forming copper-comprising conductive lines in the fabrication of integrated circuitry Grant 7,723,227 - Bian May 25, 2 | 2010-05-25 |
| Isolation trenches for memory devices Grant 7,439,157 - Bian , et al. October 21, 2 | 2008-10-21 |
| Isolation regions App 20080014710 - Bian; Zailong ; et al. | 2008-01-17 |
| Semiconductor constructions, memory arrays, electronic systems, and methods of forming semiconductor constructions App 20070045769 - Bian; Zailong ; et al. | 2007-03-01 |
| Inter-metal dielectric fill App 20060265868 - Rueger; Neal R. ; et al. | 2006-11-30 |
| Inter-metal Dielectric Fill App 20060246719 - Rueger; Neal R. ; et al. | 2006-11-02 |
| Inter-metal dielectric fill App 20060038293 - Rueger; Neal R. ; et al. | 2006-02-23 |
| Isolation trenches for memory devices App 20050287731 - Bian, Zailong ; et al. | 2005-12-29 |
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