Bhushan Singh; Nishi

Patent Applications and Registrations

Patent applications and USPTO patent grants for Bhushan Singh; Nishi.The latest application filed is for "memory test control for stacked ddr memory".

Company Profile

2.4.8

Bhushan Singh; Nishi - Bangalore IN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
In-field self-test controller for safety critical automotive use cases Grant 10,481,202 - Jain , et al. Nov	2019-11-19
Memory Test Control For Stacked Ddr Memory App 20190088348 - JAIN; Arvind ; et al.	2019-03-21
In-field Self-test Controller For Safety Critical Automotive Use Cases App 20180231609 - JAIN; Arvind ; et al.	2018-08-16
Method and apparatus for multiple memory shared collar architecture Grant 9,971,663 - Bhushan Singh , et al. May 15, 2	2018-05-15
Continuous write and read operations for memories with latencies Grant 9,972,402 - Bhushan Singh , et al. May 15, 2	2018-05-15
Multi-level Clock Gate Controls To Address Scan Mode Power Droop And Voltage Bump Requirement App 20180019733 - Tiwari; Rajesh ; et al.	2018-01-18
Continuous Write And Read Operations For Memories With Latencies App 20170309348 - Bhushan Singh; Nishi ; et al.	2017-10-26
Method and apparatus for optimized memory test status detection and debug Grant 9,711,241 - Anand , et al. July 18, 2	2017-07-18
Dynamically Configurable Shared Scan Clock Channel Architecture App 20170184665 - Tiwari; Rajesh ; et al.	2017-06-29
Enhanced Memory Built-in Self-test Architecture For De-featured Memories App 20170110204 - Kothiala; Abhinav ; et al.	2017-04-20
Method And Apparatus For Optimized Memory Test Status Detection And Debug App 20160293272 - Anand; Ashutosh ; et al.	2016-10-06
Method And Apparatus For Multiple Memory Shared Collar Architecture App 20160062864 - Bhushan Singh; Nishi ; et al.	2016-03-03

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