Bhosale; Prasad

Patent Applications and Registrations

Patent applications and USPTO patent grants for Bhosale; Prasad.The latest application filed is for "phase change memory cell with a projection liner".

Company Profile

13.11.14

Bhosale; Prasad - Albany NY
Bhosale; Prasad - Slingerlands NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Back-end-of-line interconnect structures with varying aspect ratios Grant 11,444,029 - Bhosale , et al. September 13, 2	2022-09-13
Phase Change Memory Cell With A Projection Liner App 20220181547 - OK; Injo ; et al.	2022-06-09
Interconnect Structures with Selective Barrier for BEOL Applications App 20220020638 - Bhosale; Prasad ; et al.	2022-01-20
Semiconductor tool matching and manufacturing management in a blockchain Grant 11,223,655 - Bhosale , et al. January 11, 2	2022-01-11
Back-end-of-line Interconnect Structures With Varying Aspect Ratios App 20210265277 - Bhosale; Prasad ; et al.	2021-08-26
Automated method for integrated analysis of back end of the line yield, line resistance/capacitance and process performance Grant 11,074,387 - Bhosale , et al. July 27, 2	2021-07-27
Skip via for metal interconnects Grant 10,978,388 - Amanapu , et al. April 13, 2	2021-04-13
Interconnect with self-forming wrap-all-around barrier layer Grant 10,978,342 - Huang , et al. April 13, 2	2021-04-13
Rework For Metal Interconnects Using Etch And Thermal Anneal App 20200251386 - Kind Code	2020-08-06
Interconnect with Self-Forming Wrap-All-Around Barrier Layer App 20200243383 - Huang; Huai ; et al.	2020-07-30
Rework for metal interconnects using etch and thermal anneal Grant 10,658,235 - Bhosale , et al.	2020-05-19
Skip Via For Metal Interconnects App 20200111736 - Amanapu; Hari Prasad ; et al.	2020-04-09
Automated Method For Integrated Analysis Of Back End Of The Line Yield, Line Resistance/capacitance And Process Performance App 20200089831 - Bhosale; Prasad ; et al.	2020-03-19
Automated method for integrated analysis of back end of the line yield, line resistance/capacitance and process performance Grant 10,585,998 - Bhosale , et al.	2020-03-10
Semiconductor Tool Matching And Manufacturing Management In A Blockchain App 20200053128 - Bhosale; Prasad ; et al.	2020-02-13
Rework For Metal Interconnects Using Etch And Thermal Anneal App 20190393085 - Bhosale; Prasad ; et al.	2019-12-26
Bottom electrode for MRAM applications Grant 10,461,248 - Bhosale , et al. Oc	2019-10-29
Automated method for integrated analysis of back end of the line yield, line resistance/capacitance and process performance Grant 10,303,829 - Bhosale , et al.	2019-05-28
Rework of patterned dielectric and metal hardmask films Grant 10,242,872 - Arnold , et al.	2019-03-26
Automated Method For Integrated Analysis Of Back End Of The Line Yield, Line Resistance/capacitance And Process Performance App 20180349535 - Bhosale; Prasad ; et al.	2018-12-06
Automated Method For Integrated Analysis Of Back End Of The Line Yield, Line Resistance/capacitance And Process Performance App 20180349538 - Bhosale; Prasad ; et al.	2018-12-06
Bottom electrode for MRAM applications Grant 10,096,769 - Bhosale , et al. October 9, 2	2018-10-09
Bottom Electrode For Mram Applications App 20180287051 - Bhosale; Prasad ; et al.	2018-10-04
Rework Of Patterned Dielectric And Metal Hardmask Films App 20180277369 - Arnold; John C. ; et al.	2018-09-27
Bottom Electrode For Mram Applications App 20180261759 - Bhosale; Prasad ; et al.	2018-09-13

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