Bhawmik; Sudipta

Patent Applications and Registrations

Patent applications and USPTO patent grants for Bhawmik; Sudipta.The latest application filed is for "system and method of testing through-silicon vias of a semiconductor die".

Company Profile

0.7.5

Bhawmik; Sudipta - Bridgewater NJ
Bhawmik; Sudipta - Monmouth Junction NJ
Bhawmik; Sudipta - Princeton NJ

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
System and method of testing through-silicon vias of a semiconductor die Grant 8,806,400 - Bhawmik August 12, 2	2014-08-12
System And Method Of Testing Through-silicon Vias Of A Semiconductor Die App 20140208279 - Bhawmik; Sudipta	2014-07-24
Test Controller For 3d Stacked Integrated Circuits App 20130197851 - Bhawmik; Sudipta	2013-08-01
Scan Chain Access In 3d Stacked Integrated Circuits App 20130185608 - Bhawmik; Sudipta	2013-07-18
Method and system for improving the test quality for scan-based BIST using a general test application scheme Grant 6,694,466 - Tsai , et al. February 17, 2	2004-02-17
Method for implementing a bist scheme into integrated circuits for testing RTL controller-data paths in the integrated circuits Grant 6,463,560 - Bhawmik , et al. October 8, 2	2002-10-08
Almost full-scan BIST method and system having higher fault coverage and shorter test application time Grant 6,463,561 - Bhawmik , et al. October 8, 2	2002-10-08
Hybrid algorithm for test point selection for scan-based BIST Grant 6,256,759 - Bhawmik , et al. July 3, 2	2001-07-03
Bist architecture for detecting path-delay faults in a sequential circuit Grant 6,148,425 - Bhawmik , et al. November 14, 2	2000-11-14
Method and apparatus for built-in self-test with multiple clock circuits Grant 5,680,543 - Bhawmik October 21, 1	1997-10-21

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