Bhavsar; Dilip K.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Bhavsar; Dilip K..The latest application filed is for "mechanism for concurrent testing of multiple embedded arrays".
- Bhavsar; Dilip K. - Shrewsbury MA
- Bhavsar; Dilip K. - Liverpool NY
| Patent | Date |
|---|---|
| Mechanism for concurrent testing of multiple embedded arrays App 20080098269 - Bhavsar; Dilip K. ; et al. | 2008-04-24 |
| Apparatus and method for interfacing a high speed scan-path with slow-speed test equipment Grant 6,779,142 - Bhavsar , et al. August 17, 2 | 2004-08-17 |
| Built-in test method for content addressable memories Grant 6,286,116 - Bhavsar September 4, 2 | 2001-09-04 |
| Method for cost-effective production testing of input voltage levels of the forwarded clock interface of high performance integrated circuits Grant 6,163,864 - Bhavsar , et al. December 19, 2 | 2000-12-19 |
| Architecture for system-wide standardized intra-module and inter-module fault testing Grant 5,627,842 - Brown , et al. May 6, 1 | 1997-05-06 |
| Scannable flip-flop Grant 4,669,061 - Bhavsar May 26, 1 | 1987-05-26 |
| System for polynomial division self-testing of digital networks Grant 4,498,172 - Bhavsar February 5, 1 | 1985-02-05 |
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