Bhavnagarwala; Azeez J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Bhavnagarwala; Azeez J..The latest application filed is for "hierarchically divided signal path for characterizing integrated circuits".

Company Profile

0.8.9

Bhavnagarwala; Azeez J. - Newtown CT
Bhavnagarwala; Azeez J. - Atlanta GA
Bhavnagarwala; Azeez J. - Danbury CT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Hierarchically Divided Signal Path For Characterizing Integrated Circuits App 20140257738 - Bhavnagarwala; Azeez J.	2014-09-11
Structure For Characterizing Through-silicon Vias And Methods Thereof App 20130132023 - Bhavnagarwala; Azeez J.	2013-05-23
Methods for incorporating high dielectric materials for enhanced SRAM operation and structures produced thereby Grant 7,968,450 - Bhavnagarwala , et al. June 28, 2	2011-06-28
Methods For Incorporating High Dielectric Materials For Enhanced Sram Operation And Structures Produced Thereby App 20100041227 - Bhavnagarwala; Azeez J. ; et al.	2010-02-18
Circuits and methods for providing low voltage, high performance register files Grant 7,259,986 - Bhavnagarwala , et al. August 21, 2	2007-08-21
Circuits and methods for providing low voltage, high performance register files App 20060215465 - Bhavnagarwala; Azeez J. ; et al.	2006-09-28
Methods for incorporating high k dielectric materials for enhanced SRAM operation and structures produced thereby App 20060103023 - Bhavnagarwala; Azeez J. ; et al.	2006-05-18
Digital logic with reduced leakage Grant 6,977,519 - Bhavnagarwala , et al. December 20, 2	2005-12-20
Minimum metal consumption power distribution network on a bonded die Grant 6,861,739 - Bhavnagarwala , et al. March 1, 2	2005-03-01
Method And Structure For Reducing Gate Leakage And Threshold Voltage Fluctuation In Memory Cells App 20050018518 - Bhavnagarwala, Azeez J. ; et al.	2005-01-27
Method and structure for reducing gate leakage and threshold voltage fluctuation in memory cells Grant 6,839,299 - Bhavnagarwala , et al. January 4, 2	2005-01-04
Digital logic with reduced leakage App 20040227542 - Bhavnagarwala, Azeez J. ; et al.	2004-11-18
SRAM cell with bootstrapped power line Grant 6,791,886 - Bhavnagarwala , et al. September 14, 2	2004-09-14
Self-timed read and write assist and restore circuit Grant 6,788,566 - Bhavnagarwala , et al. September 7, 2	2004-09-07
Suppression of leakage currents in VLSI logic and memory circuits Grant 6,683,805 - Joshi , et al. January 27, 2	2004-01-27
Suppression of leakage currents in VLSI logic and memory circuits App 20030147272 - Joshi, Rajiv V. ; et al.	2003-08-07

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