Bhattacharyya; Bijan
Patent Applications and Registrations
Patent applications and USPTO patent grants for Bhattacharyya; Bijan.The latest application filed is for "method and system for pedictive mosfet layout generation with reduced design cycle".
- Bhattacharyya; Bijan - Irvine CA
| Patent | Date |
|---|---|
| Method and system for predictive multi-component circuit layout generation with reduced design cycle Grant 6,839,887 - Lampaer , et al. January 4, 2 | 2005-01-04 |
| Method and system for predictive MOSFET layout generation with reduced design cycle Grant 6,728,942 - Lampaert , et al. April 27, 2 | 2004-04-27 |
| Method and system for predictive layout generation for inductors with reduced design cycle Grant 6,588,002 - Lampaert , et al. July 1, 2 | 2003-07-01 |
| Method and system for pedictive MOSFET layout generation with reduced design cycle App 20020188920 - Lampaert, Koen ; et al. | 2002-12-12 |
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