Bhattacharyya; Bidyut K.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Bhattacharyya; Bidyut K..The latest application filed is for "integrated circuit die and/or package having a variable pitch contact array for maximization of number of signal lines per routing layer".

Company Profile

0.14.2

Bhattacharyya; Bidyut K. - Phoenix AZ
Bhattacharyya; Bidyut K. - Chandler AZ
Bhattacharyya; Bidyut K. - Beaverton OR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Integrated circuit die and/or package having a variable pitch contact array for maximization of number of signal lines per routing layer Grant 7,030,479 - Siu , et al. April 18, 2	2006-04-18
Integrated circuit die and/or package having a variable pitch contact array for maximization of number of signal lines per routing layer App 20040061223 - Siu, William M. ; et al.	2004-04-01
Integrated circuit die and/or package having a variable pitch contact array for maximization of number of signal lines per routing layer Grant 6,664,620 - Siu , et al. December 16, 2	2003-12-16
Integrated Circuit Die And/or Package Having A Variable Pitch Contact Array For Maximization Of Number Of Signal Lines Per Routing Layer App 20010045633 - SIU, WILLIAM M. ; et al.	2001-11-29
Anchor provisions to prevent mold delamination in an overmolded plastic array package Grant 5,773,895 - Hassan , et al. June 30, 1	1998-06-30
Use of tantalum oxide capacitor on ceramic co-fired technology Grant 5,666,004 - Bhattacharyya , et al. September 9, 1	1997-09-09
High performance and high capacitance package with improved thermal dissipation Grant 5,608,261 - Bhattacharyya , et al. March 4, 1	1997-03-04
Advance multilayer molded plastic package using mesic technology Grant 5,556,807 - Bhattacharyya , et al. September 17, 1	1996-09-17
Power distribution lid for IC package Grant 5,475,565 - Bhattacharyya , et al. December 12, 1	1995-12-12
Integrated circuit having a two-dimensional lead grid array Grant 5,420,461 - Mallik , et al. May 30, 1	1995-05-30
De-coupling capacitor on the top of the silicon die by eutectic flip bonding Grant 5,369,545 - Bhattacharyya , et al. November 29, 1	1994-11-29
Test substation for testing semi-conductor packages Grant 5,307,012 - Bhattacharyya , et al. April 26, 1	1994-04-26
Lead grid array integrated circuit Grant 5,210,939 - Mallik , et al. May 18, 1	1993-05-18
Multi-layer molded plastic IC package Grant 4,891,687 - Mallik , et al. January 2, 1	1990-01-02
Method of making a multilayer molded plastic IC package Grant 4,835,120 - Mallik , et al. May 30, 1	1989-05-30
Process of attaching a die to a substrate using gold/silicon seed Grant 4,771,018 - Bhattacharyya , et al. September 13, 1	1988-09-13

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