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name:-0.015117168426514
name:-0.019396066665649
name:-0.0024631023406982
Bhattacharya; Subhrajit Patent Filings

Bhattacharya; Subhrajit

Patent Applications and Registrations

Patent applications and USPTO patent grants for Bhattacharya; Subhrajit.The latest application filed is for "verification of business processes using spatio-temporal data".

Company Profile
1.15.10
  • Bhattacharya; Subhrajit - Bangalore IN
  • Bhattacharya; Subhrajit - White Plains NY
  • Bhattacharya; Subhrajit - Plainsboro NJ
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Scheduling crop transplantations
Grant 10,803,412 - Bhattacharya , et al. October 13, 2
2020-10-13
Verification of business processes using spatio-temporal data
Grant 10,049,456 - Banerjee , et al. August 14, 2
2018-08-14
Verification Of Business Processes Using Spatio-temporal Data
App 20180040128 - Banerjee; Nilanjan ;   et al.
2018-02-08
Scheduling Crop Transplantations
App 20160307135 - Bhattacharya; Subhrajit ;   et al.
2016-10-20
System for using partitioned masks to build a chip
Grant 7,870,531 - Bhattacharya , et al. January 11, 2
2011-01-11
Modeling and simulating a powergated hierarchical element
Grant 7,516,424 - Barnfield , et al. April 7, 2
2009-04-07
Influence-based circuit design
Grant 7,500,207 - Bhattacharya , et al. March 3, 2
2009-03-03
Power gating techniques able to have data retention and variability immunity properties
Grant 7,479,801 - Bhattacharya January 20, 2
2009-01-20
Method for using partitioned masks to build a chip
Grant 7,469,401 - Bhattacharya , et al. December 23, 2
2008-12-23
System For Using Partitioned Masks To Build A Chip
App 20080216037 - Bhattacharya; Subhrajit ;   et al.
2008-09-04
Power gating techniques able to have data retention and variability immunity properties
Grant 7,420,388 - Bhattacharya September 2, 2
2008-09-02
Power Gating Techniques Able to Have Data Retention And Variability Immunity Properties
App 20080143431 - Bhattacharya; Subhrajit
2008-06-19
Verification of scheduling in the presence of loops using uninterpreted symbolic simulation
Grant 7,383,166 - Ashar , et al. June 3, 2
2008-06-03
Method for using partitioned masks to build a chip
App 20070196958 - Bhattacharya; Subhrajit ;   et al.
2007-08-23
Modeling and simulating a powergated hierarchical element
App 20070198237 - Barnfield; Stephen J. ;   et al.
2007-08-23
Influence-based circuit design
App 20070192752 - Bhattacharya; Subhrajit ;   et al.
2007-08-16
Power gating techniques able to have data retention and variability immunity properties
App 20060267629 - Bhattacharya; Subhrajit
2006-11-30
Power gating techniques able to have data retention and variability immunity properties
Grant 7,126,370 - Bhattacharya October 24, 2
2006-10-24
Power gating techniques able to have data retention and variability immunity properties
App 20060091913 - Bhattacharya; Subhrajit
2006-05-04
Methods and arrangements for automatically interconnecting cores in systems-on-chip
Grant 6,993,740 - Bergamaschi , et al. January 31, 2
2006-01-31
Verification of scheduling in the presence of loops using uninterpreted symbolic simulation
App 20040148150 - Ashar, Pranav ;   et al.
2004-07-29
Verification of scheduling in the presence of loops using uninterpreted symbolic simulation
Grant 6,745,160 - Ashar , et al. June 1, 2
2004-06-01
Methods and arrangements for automatic synthesis of systems-on-chip
Grant 6,477,691 - Bergamashi/Rab , et al. November 5, 2
2002-11-05
Method for verification of RTL generated from scheduled behavior in a high-level synthesis flow
Grant 6,163,876 - Ashar , et al. December 19, 2
2000-12-19
Low cost testing method for register transfer level circuits
Grant 5,748,647 - Bhattacharya , et al. May 5, 1
1998-05-05

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