Bhattacharya; Koustav

Patent Applications and Registrations

Patent applications and USPTO patent grants for Bhattacharya; Koustav.The latest application filed is for "providing matrix multiplication using vector registers in processor-based devices".

Company Profile

5.6.6

Bhattacharya; Koustav - Austin TX
Bhattacharya; Koustav - Tampa FL

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Providing flexible matrix processors for performing neural network convolution in matrix-processor-based devices Grant 10,936,943 - Verrilli , et al. March 2, 2	2021-03-02
Providing efficient floating-point operations using matrix processors in processor-based systems Grant 10,747,501 - Heddes , et al. A	2020-08-18
Providing efficient multiplication of sparse matrices in matrix-processor-based devices Grant 10,725,740 - Heddes , et al.	2020-07-28
Providing Matrix Multiplication Using Vector Registers In Processor-based Devices App 20190079903 - Dreyer; Robert ; et al.	2019-03-14
Providing Flexible Matrix Processors For Performing Neural Network Convolution In Matrix-processor-based Devices App 20190065942 - Verrilli; Colin Beaton ; et al.	2019-02-28
Providing Efficient Floating-point Operations Using Matrix Processors In Processor-based Systems App 20190065146 - Heddes; Mattheus Cornelis Antonius Adrianus ; et al.	2019-02-28
Providing Efficient Multiplication Of Sparse Matrices In Matrix-processor-based Devices App 20190065150 - Heddes; Mattheus Cornelis Antonius Adrianus ; et al.	2019-02-28
Providing flexible management of heterogeneous memory systems using spatial quality of service (QoS) tagging in processor-based systems Grant 10,055,158 - Verrilli , et al. August 21, 2	2018-08-21
PROVIDING FLEXIBLE MANAGEMENT OF HETEROGENEOUS MEMORY SYSTEMS USING SPATIAL QUALITY OF SERVICE (QoS) TAGGING IN PROCESSOR-BASED SYSTEMS App 20180081579 - Verrilli; Colin Beaton ; et al.	2018-03-22
Methodology and apparatus for reduction of soft errors in logic circuits Grant 7,944,230 - Ranganathan , et al. May 17, 2	2011-05-17
Methodology and apparatus for reduction of soft errors in logic circuits Grant 7,804,320 - Ranganathan , et al. September 28, 2	2010-09-28
Methodology and Apparatus for Reduction of Soft Errors in Logic Circuits App 20090309627 - Ranganathan; Nagarajan ; et al.	2009-12-17

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.