Bhattacharya; Debashis

Patent Applications and Registrations

Patent applications and USPTO patent grants for Bhattacharya; Debashis.The latest application filed is for "scalable autonomic message-transport with synchronization".

Company Profile

4.13.12

Bhattacharya; Debashis - Plano TX
Bhattacharya; Debashis - Hamden CT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
System and method for data warehouse engine Grant 10,817,528 - Shrivastava , et al. October 27, 2	2020-10-27
System and method for scalable distributed real-time data warehouse Grant 10,783,160 - Bhattacharya , et al. Sept	2020-09-22
System and method for real-time data warehouse Grant 10,496,622 - Chandra , et al. De	2019-12-03
Scalable autonomic message-transport with synchronization Grant 10,185,606 - Yan , et al. Ja	2019-01-22
Scalable Autonomic Message-Transport with Synchronization App 20170293512 - Yan; Peter ; et al.	2017-10-12
System and method for real time virtualization Grant 9,740,513 - Gatherer , et al. August 22, 2	2017-08-22
System and Method for Data Warehouse Engine App 20170169034 - Shrivastava; Ashish Rai ; et al.	2017-06-15
Space And Time Aware Organization And Isolation Of Components In Real Time Systems App 20170168792 - Bhattacharya; Debashis ; et al.	2017-06-15
System and Method for Scalable Distributed Real-Time Data Warehouse App 20170103076 - Bhattacharya; Debashis ; et al.	2017-04-13
System and Method for Real-Time Data Warehouse App 20170103093 - Chandra; Alex Elisa ; et al.	2017-04-13
System and Method for System on a Chip App 20160103707 - Bhattacharya; Debashis ; et al.	2016-04-14
System and Method for Real Time Virtualization App 20150355919 - Gatherer; Alan ; et al.	2015-12-10
Method And System For The Automatic Detection And Diagnosis Of A Cancer Stem Cell App 20100240087 - Bhattacharyya; Swati ; et al.	2010-09-23
Method for automated design of integrated circuits with targeted quality objectives using dynamically generated building blocks Grant 7,225,423 - Bhattacharya , et al. May 29, 2	2007-05-29
Process for automated generation of design-specific complex functional blocks to improve quality of synthesized digital integrated circuits in CMOS using altering process Grant 7,003,738 - Bhattacharya , et al. February 21, 2	2006-02-21
Logic circuit having a functionally redundant transistor network Grant 6,938,223 - Boppana , et al. August 30, 2	2005-08-30
Context-sensitive constraint driven uniquification and characterization of standard cells Grant 6,782,514 - Bhattacharya , et al. August 24, 2	2004-08-24
Context-sensitive constraint driven uniquification and characterization of standard cells App 20030140319 - Bhattacharya, Debashis ; et al.	2003-07-24
Digital logic circuits used to design integrated circuits App 20020162078 - Boppana, Vamsi ; et al.	2002-10-31
Snoopy test access port architecture for electronic circuits including embedded core with built-in test access port Grant 6,425,100 - Bhattacharya July 23, 2	2002-07-23
Method for automated design of integrated circuits with targeted quality objectives using dynamically generated building blocks App 20020069396 - Bhattacharya, Debashis ; et al.	2002-06-06
Process for automated generation of design-specific complex functional blocks to improve quality of synthesized digital integrated circuits in CMOS App 20020053063 - Bhattacharya, Debashis ; et al.	2002-05-02
Snoopy test access port architecture for electronic circuits including embedded core having test access port with instruction driven wake-up Grant 6,381,717 - Bhattacharya April 30, 2	2002-04-30
Hierarchical test access port architecture for electronic circuits including embedded core having built-in test access port Grant 6,378,090 - Bhattacharya April 23, 2	2002-04-23
Counterflow pipeline processor architecture for semi-custom application specific IC's Grant 5,704,054 - Bhattacharya December 30, 1	1997-12-30

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