Bhatkar; Mahesh

Patent Applications and Registrations

Patent applications and USPTO patent grants for Bhatkar; Mahesh.The latest application filed is for "embedded mram in interconnects and method for producing the same".

Company Profile

7.13.10

Bhatkar; Mahesh - Singapore SG
Bhatkar; Mahesh - Singpaore SG

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Two pass MRAM dummy solution Grant 10,566,384 - Yi , et al. Feb	2020-02-18
Device without zero mark layer Grant 10,553,488 - Gong , et al. Fe	2020-02-04
Embedded MRAM in interconnects and method for producing the same Grant 10,483,461 - Yi , et al. Nov	2019-11-19
Embedded Mram In Interconnects And Method For Producing The Same App 20190326509 - YI; Wanbing ; et al.	2019-10-24
MRAM device with improved seal ring and method for producing the same Grant 10,381,403 - Jiang , et al. A	2019-08-13
Two Pass Mram Dummy Solution App 20190074434 - YI; Wanbing ; et al.	2019-03-07
Integrated circuits with vertical capacitors and methods for producing the same Grant 10,217,794 - Tan , et al. Feb	2019-02-26
Two pass MRAM dummy solution Grant 10,158,066 - Yi , et al. Dec	2018-12-18
Two Pass Mram Dummy Solution App 20180358546 - YI; Wanbing ; et al.	2018-12-13
Integrated Circuits With Vertical Capacitors And Methods For Producing The Same App 20180342556 - Tan; Juan Boon ; et al.	2018-11-29
Robust chamfer design for seal ring Grant 10,121,755 - Bhatkar , et al. November 6, 2	2018-11-06
Integrated circuits with magnetic tunnel junction memory cells and methods for producing the same Grant 10,062,733 - Yi , et al. August 28, 2	2018-08-28
Integrated circuits with aluminum via structures and methods for fabricating the same Grant 9,917,027 - Yi , et al. March 13, 2	2018-03-13
Device Without Zero Mark Layer App 20180012800 - GONG; Shunqiang ; et al.	2018-01-11
Device without zero mark layer Grant 9,773,702 - Gong , et al. September 26, 2	2017-09-26
Semiconductor chips with seal rings and electronic test structures, semiconductor wafers including the semiconductor chips, and methods for fabricating the same Grant 9,728,474 - Yi , et al. August 8, 2	2017-08-08
Integrated Circuits With Aluminum Via Structures And Methods For Fabricating The Same App 20170194229 - Yi; Wanbing ; et al.	2017-07-06
Integrated circuits including magnetic core inductors and methods for fabricating the same Grant 9,613,897 - Bhatkar , et al. April 4, 2	2017-04-04
Device Without Zero Mark Layer App 20160190041 - Gong; Shunqiang ; et al.	2016-06-30
Integrated Circuits Including Magnetic Core Inductors And Methods For Fabricating The Same App 20160133565 - Bhatkar; Mahesh ; et al.	2016-05-12
Pad Solutions For Reliable Bonds App 20150061156 - JIANG; Yi ; et al.	2015-03-05
Dielectric posts in metal layers Grant 8,957,523 - Zhang , et al. February 17, 2	2015-02-17
Dielectric Posts In Metal Layers App 20140191407 - ZHANG; Fan ; et al.	2014-07-10

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.