Bhatia; Harsaran S.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Bhatia; Harsaran S..The latest application filed is for "programmable random logic arrays using pn isolation".
- Bhatia; Harsaran S. - Hopewell Junction NY
- Bhatia; Harsaran S. - Wappingers Falls NY
- Bhatia; Harsaran S. - Wappinger Falls NY
- Bhatia; Harsaran S. - Fishkill NY
| Patent | Date |
|---|---|
| Programmable random logic arrays using PN isolation Grant 7,704,802 - Bhatia , et al. April 27, 2 | 2010-04-27 |
| Intelligent sensor network Grant 7,701,874 - Kline , et al. April 20, 2 | 2010-04-20 |
| Programmable random logic arrays using PN isolation Grant 7,420,248 - Bhatia , et al. September 2, 2 | 2008-09-02 |
| Programmable Random Logic Arrays Using Pn Isolation App 20080032460 - Bhatia; Harsaran S. ; et al. | 2008-02-07 |
| Nested design approach Grant 7,325,213 - Bhatia , et al. January 29, 2 | 2008-01-29 |
| Programmable random logic arrays using PN isolation App 20070045733 - Bhatia; Harsaran S. ; et al. | 2007-03-01 |
| Intelligent Sensor Network App 20060280129 - Kline; Eric V. ; et al. | 2006-12-14 |
| Nested Design Approach App 20050278674 - Bhatia, Harsaran S. ; et al. | 2005-12-15 |
| Embedded inductor and method of making Grant 6,975,199 - Long , et al. December 13, 2 | 2005-12-13 |
| Method of forming a dielectric substrate having a multiturn inductor Grant 6,931,712 - Long , et al. August 23, 2 | 2005-08-23 |
| Embedded Inductor And Method Of Making App 20050150106 - Long, David Clifford ; et al. | 2005-07-14 |
| MLC frequency selective circuit structures Grant 6,806,793 - Bhatia , et al. October 19, 2 | 2004-10-19 |
| MLC frequency selective circuit structures App 20040113721 - Bhatia, Harsaran S. ; et al. | 2004-06-17 |
| Embedded inductor and method of making App 20030112114 - Long, David Clifford ; et al. | 2003-06-19 |
| Substrate Design Of A Chip Using A Generic Substrate Design App 20030047352 - Bhatia, Harsaran S. ; et al. | 2003-03-13 |
| Method and circuit for electrical testing of isolation resistance of large capacitance network App 20030042910 - Bhatia, Harsaran S. ; et al. | 2003-03-06 |
| Schottky diode having limited area self-aligned guard ring and method for making same Grant 4,796,069 - Anantha , et al. January 3, 1 | 1989-01-03 |
| Electronic EC for minimizing EC pads Grant 4,746,815 - Bhatia , et al. May 24, 1 | 1988-05-24 |
| Structure for contacting a narrow width PN junction region Grant 4,712,125 - Bhatia , et al. * December 8, 1 | 1987-12-08 |
| Method for making Schottky diode having limited area self-aligned guard ring Grant 4,691,435 - Anantha , et al. September 8, 1 | 1987-09-08 |
| Method and resulting structure for selective multiple base width transistor structures Grant 4,535,531 - Bhatia , et al. * August 20, 1 | 1985-08-20 |
| Method for contacting a narrow width PN junction region Grant 4,507,171 - Bhatia , et al. March 26, 1 | 1985-03-26 |
| Method for making high sheet resistivity resistors Grant 4,464,212 - Bhatia , et al. August 7, 1 | 1984-08-07 |
| High density memory cell Grant 4,427,989 - Anantha , et al. January 24, 1 | 1984-01-24 |
| Method of planarizing silicon dioxide in semiconductor devices Grant 4,389,281 - Anantha , et al. June 21, 1 | 1983-06-21 |
| Method for avoiding residue on a vertical walled mesa Grant 4,389,294 - Anantha , et al. June 21, 1 | 1983-06-21 |
| Self aligned method for making bipolar transistor having minimum base to emitter contact spacing Grant 4,252,582 - Anantha , et al. February 24, 1 | 1981-02-24 |
| High performance bipolar device and method for making same Grant 4,236,294 - Anantha , et al. December 2, 1 | 1980-12-02 |
| Method for fabricating vertical NPN and PNP structures and the resulting product Grant 4,214,315 - Anantha , et al. July 22, 1 | 1980-07-22 |
| High performance bipolar device and method for making same Grant 4,160,991 - Anantha , et al. July 10, 1 | 1979-07-10 |
| Method for fabrication vertical NPN and PNP structures utilizing ion-implantation Grant 4,159,915 - Anantha , et al. July 3, 1 | 1979-07-03 |
| Push-pull Line Driver Circuit Grant 3,757,138 - Bhatia , et al. September 4, 1 | 1973-09-04 |
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