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Patent applications and USPTO patent grants for Bhardwaj; Sarvesh.The latest application filed is for "clock-reconvergence pessimism removal in hierarchical static timing analysis".
Patent | Date |
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Clock-reconvergence pessimism removal in hierarchical static timing analysis Grant 8,813,011 - Bhardwaj , et al. August 19, 2 | 2014-08-19 |
Reducing memory used to store totals in static timing analysis Grant 8,775,855 - Bhardwaj , et al. July 8, 2 | 2014-07-08 |
Clock-Reconvergence Pessimism Removal In Hierarchical Static Timing Analysis App 20130246991 - Bhardwaj; Sarvesh ;   et al. | 2013-09-19 |
Clock-reconvergence pessimism removal in hierarchical static timing analysis Grant 8,434,040 - Bhardwaj , et al. April 30, 2 | 2013-04-30 |
Clock-Reconvergence Pessimism Removal In Hierarchical Static Timing Analysis App 20120278778 - Bhardwaj; Sarvesh ;   et al. | 2012-11-01 |
Reducing Memory Used To Store Totals In Static Timing Analysis App 20120278647 - Bhardwaj; Sarvesh ;   et al. | 2012-11-01 |
Method of evaluating integrated circuit system performance using orthogonal polynomials Grant 7,630,852 - Ghanta , et al. December 8, 2 | 2009-12-08 |
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