Bhalerao; Abhijeet

Patent Applications and Registrations

Patent applications and USPTO patent grants for Bhalerao; Abhijeet.The latest application filed is for "systems and methods for expediting design of physical components through use of computationally efficient virtual simulations".

Company Profile

1.11.12

Bhalerao; Abhijeet - Willowbrook IL
Bhalerao; Abhijeet - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Systems and methods for expediting design of physical components through use of computationally efficient virtual simulations Grant 11,295,046 - Singh , et al. April 5, 2	2022-04-05
Systems And Methods For Expediting Design Of Physical Components Through Use Of Computationally Efficient Virtual Simulations App 20200327204 - Singh; Samrendra K ; et al.	2020-10-15
Systems And Methods For Expediting Design Of Physical Components Through Use Of Computationally Efficient Virtual Simulations App 20200327209 - Singh; Samrendra K. ; et al.	2020-10-15
System, method and apparatus for preventing data loss due to memory defects using latches Grant 9,983,920 - Bhalerao , et al. May 29, 2	2018-05-29
Data folding in 3D nonvolatile memory Grant 9,858,009 - Bhalerao , et al. January 2, 2	2018-01-02
Partial bad block detection and re-use using EPWR for block based architectures Grant 9,804,922 - Kochar , et al. October 31, 2	2017-10-31
Partially-bad block operation in 3-D nonvolatile memory Grant 9,760,303 - Ea , et al. September 12, 2	2017-09-12
Non-volatile memory systems with multi-write direction memory units Grant 9,728,262 - Baran , et al. August 8, 2	2017-08-08
Non-Volatile Memory Systems with Multi-Write Direction Memory Units App 20170125104 - Baran; Ivan ; et al.	2017-05-04
Data Folding in 3D Nonvolatile Memory App 20170115884 - Bhalerao; Abhijeet ; et al.	2017-04-27
Partially-Bad Block Operation in 3-D Nonvolatile Memory App 20170090762 - Ea; Dennis S. ; et al.	2017-03-30
Initialization techniques for multi-level memory cells using multi-pass programming Grant 9,460,780 - Lee , et al. October 4, 2	2016-10-04
Memory system performance configuration Grant 9,442,842 - Yadav , et al. September 13, 2	2016-09-13
System, Method and Apparatus for Preventing Data Loss Due to Memory Defects Using Latches App 20160253231 - Bhalerao; Abhijeet ; et al.	2016-09-01
Initialization Techniques For Multi-level Memory Cells Using Multi-pass Programming App 20160211014 - Lee; Aaron ; et al.	2016-07-21
System, method and apparatus for preventing data loss due to memory defects using latches Grant 9,372,629 - Bhalerao , et al. June 21, 2	2016-06-21
Partial Bad Block Detection And Re-use Using Epwr For Block Based Architectures App 20160019111 - Kochar; Mrinal ; et al.	2016-01-21
Adaptive EPWR (enhanced post write read) scheduling Grant 9,235,470 - Bhalerao , et al. January 12, 2	2016-01-12
System, Method And Apparatus For Preventing Data Loss Due To Memory Defects Using Latches App 20150355852 - Bhalerao; Abhijeet ; et al.	2015-12-10
Adaptive Epwr (enhanced Post Write Read) Scheduling App 20150100851 - Bhalerao; Abhijeet ; et al.	2015-04-09
Memory System Performance Configuration App 20150052289 - Yadav; Preeti ; et al.	2015-02-19

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