loadpatents
name:-0.012693166732788
name:-0.027240037918091
name:-0.00079011917114258
Bhagavatheeswaran; Gayathri A. Patent Filings

Bhagavatheeswaran; Gayathri A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Bhagavatheeswaran; Gayathri A..The latest application filed is for "memory interface receivers having pulsed control of input signal attenuation networks".

Company Profile
0.16.11
  • Bhagavatheeswaran; Gayathri A. - Austin TX
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Memory interface receivers having pulsed control of input signal attenuation networks
Grant 9,356,577 - Sanchez , et al. May 31, 2
2016-05-31
Memory Interface Receivers Having Pulsed Control Of Input Signal Attenuation Networks
App 20160049922 - Sanchez; Hector ;   et al.
2016-02-18
Phase locked loop with burn-in mode
Grant 9,209,819 - Tang , et al. December 8, 2
2015-12-08
Voltage translation circuit
Grant 8,766,680 - Tang , et al. July 1, 2
2014-07-01
Phase Locked Loop With Burn-in Mode
App 20140084974 - TANG; XINGHAI ;   et al.
2014-03-27
Voltage Translation Circuit
App 20140084975 - TANG; XINGHAI ;   et al.
2014-03-27
AC coupled level shifter
Grant 8,629,707 - Sanchez , et al. January 14, 2
2014-01-14
Phase locked loop with power supply control
Grant 8,558,591 - Sanchez , et al. October 15, 2
2013-10-15
Phase locked loop device and method thereof
Grant 8,509,370 - Bhagavatheeswaran , et al. August 13, 2
2013-08-13
Phase locked loop device and method thereof
Grant 8,324,882 - Bhagavatheeswaran , et al. December 4, 2
2012-12-04
Phase-locked loop system with a phase-error spreading circuit
Grant 8,094,769 - Bhagavatheeswaran , et al. January 10, 2
2012-01-10
Phase-locked loop having a feedback clock detector circuit and method therefor
Grant 8,018,259 - Sanchez , et al. September 13, 2
2011-09-13
Phase-locked Loop Having A Feedback Clock Detector Circuit And Method Therefor
App 20110181326 - Sanchez; Hector ;   et al.
2011-07-28
Phase Locked Loop Device And Method Thereof
App 20100308793 - Bhagavatheeswaran; Gayathri A. ;   et al.
2010-12-09
Phase Locked Loop Device And Method Thereof
App 20100310030 - Bhagavatheeswaran; Gayathri A. ;   et al.
2010-12-09
Phase-locked Loop System With A Phase-error Spreading Circuit
App 20100020910 - BHAGAVATHEESWARAN; Gayathri A. ;   et al.
2010-01-28
System and circuit for controlling well biasing and method thereof
Grant 6,753,719 - Bhagavatheeswaran , et al. June 22, 2
2004-06-22
System and circuit for controlling well biasing and method thereof
App 20040036525 - Bhagavatheeswaran, Gayathri A. ;   et al.
2004-02-26

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed