loadpatents
Patent applications and USPTO patent grants for Bhagavat; Milind.The latest application filed is for "high density cross link die with polymer routing layer".
Patent | Date |
---|---|
Multiple-die integrated circuit with integrated voltage regulator Grant 11,011,495 - Bhagavat , et al. May 18, 2 | 2021-05-18 |
High density cross link die with polymer routing layer Grant 10,923,430 - Lin , et al. February 16, 2 | 2021-02-16 |
High Density Cross Link Die With Polymer Routing Layer App 20200411443 - Guo; Fei ;   et al. | 2020-12-31 |
Circuit Board With Compact Passive Component Arrangement App 20200185366 - Bhagavat; Milind ;   et al. | 2020-06-11 |
Multiple-die Integrated Circuit With Integrated Voltage Regulator App 20200066677 - Bhagavat; Milind ;   et al. | 2020-02-27 |
Offset-aligned three-dimensional integrated circuit Grant 10,573,630 - Wilkerson , et al. Feb | 2020-02-25 |
Offset-aligned Three-dimensional Integrated Circuit App 20190326272 - Wilkerson; Brett P. ;   et al. | 2019-10-24 |
MEMS in-plane resonators Grant 8,593,155 - Sparks , et al. November 26, 2 | 2013-11-26 |
High Noise Immunity and High Spatial Resolution Mutual Capacitive Touch Panel App 20120299868 - Bhagavat; Milind ;   et al. | 2012-11-29 |
MEMS In-Plane Resonators App 20120112765 - Sparks; Andrew ;   et al. | 2012-05-10 |
Method for capping a MEMS wafer Grant 8,058,144 - Bhagavat , et al. November 15, 2 | 2011-11-15 |
Capped wafer method and apparatus Grant 7,981,723 - Yang , et al. July 19, 2 | 2011-07-19 |
Capped Wafer Method and Apparatus App 20100117221 - Yang; Xue'en ;   et al. | 2010-05-13 |
Method for Capping a MEMS Wafer App 20090294879 - Bhagavat; Milind ;   et al. | 2009-12-03 |
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