Beyer; Sven

Patent Applications and Registrations

Patent applications and USPTO patent grants for Beyer; Sven.The latest application filed is for "transistor element including a buried insulating layer having enhanced functionality".

Company Profile

4.108.97

Beyer; Sven - Dresden DE
Beyer; Sven - Munich N/A DE
Beyer; Sven - Fishkill NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Transistor element including a buried insulating layer having enhanced functionality Grant 10,319,732 - Richter , et al.	2019-06-11
Communicating optical signals between stacked dies Grant 10,283,490 - Beyer , et al.	2019-05-07
Flash memory device Grant 10,249,633 - Richter , et al.	2019-04-02
Ferro-FET device with buried buffer/ferroelectric layer stack Grant 10,163,933 - Richter , et al. Dec	2018-12-25
Transistor Element Including A Buried Insulating Layer Having Enhanced Functionality App 20180366484 - Richter; Ralf ; et al.	2018-12-20
Methods for forming integrated circuits that include a dummy gate structure Grant 10,157,996 - Smith , et al. Dec	2018-12-18
NVM device in SOI technology and method of fabricating an according device Grant 10,084,057 - Beyer , et al. September 25, 2	2018-09-25
Programmable logic elements and methods of operating the same Grant 10,033,383 - Richter , et al. July 24, 2	2018-07-24
Flash Memory Device App 20180108668 - Richter; Ralf ; et al.	2018-04-19
Nvm Device In Soi Technology And Method Of Fabricating An According Device App 20180053832 - Beyer; Sven ; et al.	2018-02-22
Flash memory device Grant 9,871,050 - Richter , et al. January 16, 2	2018-01-16
Die-die Stacking App 20180012877 - Beyer; Sven ; et al.	2018-01-11
Methods For Forming Integrated Circuits That Include A Dummy Gate Structure App 20170345914 - Smith; Elliot John ; et al.	2017-11-30
Die-die stacking Grant 9,806,067 - Beyer , et al. October 31, 2	2017-10-31
Integrated circuit including a dummy gate structure and method for the formation thereof Grant 9,793,372 - Smith , et al. October 17, 2	2017-10-17
Semiconductor device with a memory device and a high-K metal gate transistor Grant 9,754,951 - Richter , et al. September 5, 2	2017-09-05
Semiconductor structure including a nonvolatile memory cell and method for the formation thereof Grant 9,711,513 - Zaka , et al. July 18, 2	2017-07-18
Capacitor structure and method of forming a capacitor structure Grant 9,698,179 - Smith , et al. July 4, 2	2017-07-04
Semiconductor Device With A Memory Device And A High-k Metal Gate Transistor App 20170125432 - Richter; Ralf ; et al.	2017-05-04
BULEX contacts in advanced FDSOI techniques Grant 9,608,112 - Smith , et al. March 28, 2	2017-03-28
Wafer With Soi Structure Having A Buried Insulating Multilayer Structure And Semiconductor Device Structure App 20170077314 - Smith; Elliot John ; et al.	2017-03-16
Wafer with SOI structure having a buried insulating multilayer structure and semiconductor device structure Grant 9,590,118 - Smith , et al. March 7, 2	2017-03-07
Method including a formation of a control gate of a nonvolatile memory cell and semiconductor structure Grant 9,583,640 - Richter , et al. February 28, 2	2017-02-28
Semiconductor Structure Including A Nonvolatile Memory Cell And Method For The Formation Thereof App 20170047336 - Zaka; Alban ; et al.	2017-02-16
Capacitor Structure And Method Of Forming A Capacitor Structure App 20170040354 - Smith; Elliot John ; et al.	2017-02-09
Bulex Contacts In Advanced Fdsoi Techniques App 20170040450 - Smith; Elliot John ; et al.	2017-02-09
Die-die Stacking App 20170025398 - Beyer; Sven ; et al.	2017-01-26
Method including a formation of a control gate of a nonvolatile memory cell and semiconductor structure including a nonvolatile memory cell Grant 9,548,312 - Beyer , et al. January 17, 2	2017-01-17
Semiconductor device comprising a stacked die configuration including an integrated peltier element Grant 9,490,189 - Griebenow , et al. November 8, 2	2016-11-08
Meander Resistor App 20160141393 - Hoentschel; Jan ; et al.	2016-05-19
Robust Post-gate Spacer Processing And Device App 20160071954 - HOENTSCHEL; Jan ; et al.	2016-03-10
Enhanced patterning uniformity of gate electrodes of a semiconductor device by late gate doping Grant 9,281,200 - Thees , et al. March 8, 2	2016-03-08
Meander Resistor App 20150333057 - Hoentschel; Jan ; et al.	2015-11-19
Contact bars with reduced fringing capacitance in a semiconductor device Grant 9,184,095 - Scheiper , et al. November 10, 2	2015-11-10
Methods for fabricating FinFET integrated circuits using laser interference lithography techniques Grant 9,123,825 - Beyer , et al. September 1, 2	2015-09-01
Methods for fabricating integrated circuits with fully silicided gate electrode structures Grant 9,123,827 - Beyer , et al. September 1, 2	2015-09-01
Methods For Fabricating Integrated Circuits With Fully Silicided Gate Electrode Structures App 20150200142 - Beyer; Sven ; et al.	2015-07-16
Methods For Fabricating Finfet Integrated Circuits Using Laser Interference Lithography Techniques App 20150200140 - Beyer; Sven ; et al.	2015-07-16
Semiconductor Device Including A Transistor Having A Low Doped Drift Region And Method For The Formation Thereof App 20150162439 - Hoentschel; Jan ; et al.	2015-06-11
Field effect transistors for a flash memory comprising a self-aligned charge storage region Grant 9,054,207 - Scheiper , et al. June 9, 2	2015-06-09
Gate electrode with a shrink spacer Grant 9,040,405 - Hasche , et al. May 26, 2	2015-05-26
Superior Integrity Of A High-k Gate Stack By Forming A Controlled Undercut On The Basis Of A Wet Chemistry App 20150137270 - Beyer; Sven ; et al.	2015-05-21
Gate Electrode With A Shrink Spacer App 20150091068 - Hasche; Tom ; et al.	2015-04-02
Method of forming spacers that provide enhanced protection for gate electrode structures Grant 8,987,104 - Baars , et al. March 24, 2	2015-03-24
Superior integrity of a high-K gate stack by forming a controlled undercut on the basis of a wet chemistry Grant 8,951,901 - Beyer , et al. February 10, 2	2015-02-10
Enhancing integrity of a high-K gate stack by protecting a liner at the gate bottom during gate head exposure Grant 8,932,930 - Beyer , et al. January 13, 2	2015-01-13
Superior integrity of high-k metal gate stacks by capping STI regions Grant 8,916,433 - Scheiper , et al. December 23, 2	2014-12-23
Method Of Forming A Semiconductor Structure Including An Implantation Of Ions Into A Layer Of Spacer Material App 20140256137 - Richter; Ralf ; et al.	2014-09-11
Semiconductor Device Comprising A Stacked Die Configuration Including An Integrated Peltier Element App 20140238045 - Griebenow; Uwe ; et al.	2014-08-28
Method of forming a semiconductor structure including an implantation of ions into a layer of spacer material Grant 8,815,741 - Richter , et al. August 26, 2	2014-08-26
Multiple gate transistor having homogenously silicided fin end portions Grant 8,791,509 - Beyer , et al. July 29, 2	2014-07-29
Transistors comprising high-K metal gate electrode structures and embedded strain-inducing semiconductor alloys formed in a late stage Grant 8,786,027 - Griebenow , et al. July 22, 2	2014-07-22
Semiconductor device comprising a stacked die configuration including an integrated Peltier element Grant 8,759,960 - Griebenow , et al. June 24, 2	2014-06-24
Enhanced confinement of sensitive materials of a high-K metal gate electrode structure Grant 8,748,281 - Hoentschel , et al. June 10, 2	2014-06-10
Method for making high-K metal gate electrode structures by separate removal of placeholder materials Grant 8,735,270 - Hempel , et al. May 27, 2	2014-05-27
Gate electrodes of a semiconductor device formed by a hard mask and double exposure in combination with a shrink spacer Grant 8,728,924 - Beyer , et al. May 20, 2	2014-05-20
Method of forming a semiconductor structure including a wet etch process for removing silicon nitride Grant 8,716,136 - Reimer , et al. May 6, 2	2014-05-06
Method Of Forming A Semiconductor Structure Including A Wet Etch Process For Removing Silicon Nitride App 20140113455 - Reimer; Berthold ; et al.	2014-04-24
High-K metal gate electrode structures formed at different process stages of a semiconductor device Grant 8,669,151 - Hoentschel , et al. March 11, 2	2014-03-11
High-K metal gate electrode structures formed by early cap layer adaptation Grant 8,664,057 - Pal , et al. March 4, 2	2014-03-04
High-k metal gate electrode structures formed by separate removal of placeholder materials using a masking regime prior to gate patterning Grant 8,652,956 - Beyer , et al. February 18, 2	2014-02-18
Work function adjustment in a high-K gate electrode structure after transistor fabrication by using lanthanum Grant 8,653,605 - Carter , et al. February 18, 2	2014-02-18
Work Function Adjustment In A High-k Gate Electrode Structure After Transistor Fabrication By Using Lanthanum App 20140015058 - Carter; Richard ; et al.	2014-01-16
Field Effect Transistors For A Flash Memory Comprising A Self-aligned Charge Storage Region App 20130299891 - Scheiper; Thilo ; et al.	2013-11-14
Method For Forming A Semiconductor Device Having Raised Drain And Source Regions And Corresponding Semiconductor Device App 20130292774 - Hoentschel; Jan ; et al.	2013-11-07
High-k Metal Gate Electrode Structures Formed By Separate Removal Of Placeholder Materials In Transistors Of Different Conductivity Type App 20130273729 - Hempel; Klaus ; et al.	2013-10-17
Transistors Comprising High-k Metal Gate Electrode Structures And Embedded Strain-inducing Semiconductor Alloys Formed In A Late Stage App 20130240988 - Griebenow; Uwe ; et al.	2013-09-19
Predoped semiconductor material for a high-K metal gate electrode structure of P- and N-channel transistors Grant 8,536,036 - Beyer , et al. September 17, 2	2013-09-17
Maintaining integrity of a high-K gate stack by passivation using an oxygen plasma Grant 8,524,591 - Beyer , et al. September 3, 2	2013-09-03
Adjusting threshold voltage for sophisticated transistors by diffusing a gate dielectric cap layer material prior to gate dielectric stabilization Grant 8,525,289 - Carter , et al. September 3, 2	2013-09-03
Field effect transistors for a flash memory comprising a self-aligned charge storage region Grant 8,507,348 - Scheiper , et al. August 13, 2	2013-08-13
Optical signal transfer in a semiconductor device by using monolithic opto-electronic components Grant 8,508,008 - Griebenow , et al. August 13, 2	2013-08-13
Enhancing Integrity Of A High-k Gate Stack By Protecting A Liner At The Gate Bottom During Gate Head Exposure App 20130157432 - BEYER; Sven ; et al.	2013-06-20
Transistors comprising high-K metal gate electrode structures and embedded strain-inducing semiconductor alloys formed in a late stage Grant 8,455,314 - Griebenow , et al. June 4, 2	2013-06-04
Semiconductor device comprising metal gates and semiconductor resistors formed on the basis of a replacement gate approach Grant 8,450,163 - Beyer , et al. May 28, 2	2013-05-28
Patterning of Sensitive Metal-Containing Layers With Superior Mask Material Adhesion by Providing a Modified Surface Layer App 20130126984 - Reimer; Berthold ; et al.	2013-05-23
Uniform high-k metal gate stacks by adjusting threshold voltage for sophisticated transistors by diffusing a metal species prior to gate patterning Grant 8,445,344 - Carter , et al. May 21, 2	2013-05-21
Replacement gate approach based on a reverse offset spacer applied prior to work function metal deposition Grant 8,409,942 - Scheiper , et al. April 2, 2	2013-04-02
Performance enhancement in PFET transistors comprising high-k metal gate stack by increasing dopant confinement Grant 8,404,550 - Scheiper , et al. March 26, 2	2013-03-26
Maintaining integrity of a high-K gate stack by an offset spacer used to determine an offset of a strain-inducing semiconductor alloy Grant 8,378,432 - Carter , et al. February 19, 2	2013-02-19
High-k Metal Gate Electrode Structures Formed By Early Cap Layer Adaptation App 20130034942 - Pal; Rohit ; et al.	2013-02-07
Method for forming CMOS transistors having metal-containing gate electrodes formed on a high-K gate dielectric material Grant 8,367,495 - Beyer , et al. February 5, 2	2013-02-05
Equivalence verification between transaction level models and RTL at the example to processors Grant 8,359,561 - Bormann , et al. January 22, 2	2013-01-22
Work function adjustment in high-k gate stacks for devices of different threshold voltage Grant 8,357,604 - Hoentschel , et al. January 22, 2	2013-01-22
Work function adjustment in a high-k gate electrode structure after transistor fabrication by using lanthanum Grant 8,343,837 - Carter , et al. January 1, 2	2013-01-01
Increased depth of drain and source regions in complementary transistors by forming a deep drain and source region prior to a cavity etch Grant 8,338,894 - Griebenow , et al. December 25, 2	2012-12-25
Enhancing integrity of a high-k gate stack by protecting a liner at the gate bottom during gate head exposure Grant 8,329,549 - Beyer , et al. December 11, 2	2012-12-11
Strain memorization in strained SOI substrates of semiconductor devices Grant 8,329,531 - Hoentschel , et al. December 11, 2	2012-12-11
Performance enhancement in transistors comprising high-k metal gate stack by an early extension implantation Grant 8,318,564 - Scheiper , et al. November 27, 2	2012-11-27
Contacts and vias of a semiconductor device formed by a hard mask and double exposure Grant 8,318,598 - Beyer , et al. November 27, 2	2012-11-27
Method of Forming Spacers That Provide Enhanced Protection for Gate Electrode Structures App 20120292671 - Baars; Peter ; et al.	2012-11-22
Dual Cavity Etch for Embedded Stressor Regions App 20120292637 - Beyer; Sven ; et al.	2012-11-22
Short Channel Transistor With Reduced Length Variation By Using Amorphous Electrode Material During Implantation App 20120280277 - Scheiper; Thilo ; et al.	2012-11-08
Semiconductor device comprising a metal gate stack of reduced height and method of forming the same Grant 8,293,610 - Beyer , et al. October 23, 2	2012-10-23
High-k Metal Gate Electrode Structures Formed By Separate Removal Of Placeholder Materials Using A Masking Regime Prior To Gate Patterning App 20120261765 - Beyer; Sven ; et al.	2012-10-18
Enhanced etch stop capability during patterning of silicon nitride including layer stacks by providing a chemically formed oxide layer during semiconductor processing Grant 8,283,232 - Beyer , et al. October 9, 2	2012-10-09
Superior Integrity of High-K Metal Gate Stacks by Capping STI Regions App 20120223407 - Scheiper; Thilo ; et al.	2012-09-06
Strain engineering in three-dimensional transistors based on globally strained semiconductor base layers Grant 8,247,275 - Hoentschel , et al. August 21, 2	2012-08-21
Short channel transistor with reduced length variation by using amorphous electrode material during implantation Grant 8,241,977 - Scheiper , et al. August 14, 2	2012-08-14
Adjusting Threshold Voltage For Sophisticated Transistors By Diffusing A Gate Dielectric Cap Layer Material Prior To Gate Dielectric Stabilization App 20120193727 - Carter; Richard ; et al.	2012-08-02
High-K metal gate electrode structures formed by separate removal of placeholder materials using a masking regime prior to gate patterning Grant 8,232,188 - Beyer , et al. July 31, 2	2012-07-31
Enhanced Patterning Uniformity of Gate Electrodes of a Semiconductor Device by Late Gate Doping App 20120156865 - Thees; Hans-Juergen ; et al.	2012-06-21
Patterning of a Stressed Dielectric Material in a Contact Level Without Using an Underlying Etch Stop Layer App 20120156839 - Scheiper; Thilo ; et al.	2012-06-21
Adjusting threshold voltage for sophisticated transistors by diffusing a gate dielectric cap layer material prior to gate dielectric stabilization Grant 8,198,192 - Carter , et al. June 12, 2	2012-06-12
Transistors comprising high-k metal gate electrode structures and adapted channel semiconductor materials Grant 8,198,152 - Beyer , et al. June 12, 2	2012-06-12
Superior Integrity of a High-K Gate Stack by Forming a Controlled Undercut on the Basis of a Wet Chemistry App 20120086056 - Beyer; Sven ; et al.	2012-04-12
Transistor including a high-K metal gate electrode structure formed on the basis of a simplified spacer regime Grant 8,143,132 - Hoentschel , et al. March 27, 2	2012-03-27
Semiconductor device comprising isolation trenches inducing different types of strain Grant 8,138,571 - Schwan , et al. March 20, 2	2012-03-20
Gate Electrodes of a Semiconductor Device Formed by a Hard Mask and Double Exposure in Combination with a Shrink Spacer App 20120049286 - Beyer; Sven ; et al.	2012-03-01
Transistors Comprising High-K Metal Gate Electrode Structures and Embedded Strain-Inducing Semiconductor Alloys Formed in a Late Stage App 20120025266 - Griebenow; Uwe ; et al.	2012-02-02
Semiconductor Device Comprising a Stacked Die Configuration Including an Integrated Peltier Element App 20110291269 - Griebenow; Uwe ; et al.	2011-12-01
Semiconductor Device Comprising Metal Gates and Semiconductor Resistors Formed on the Basis of a Replacement Gate Approach App 20110266633 - Beyer; Sven ; et al.	2011-11-03
Maintaining Integrity of a High-K Gate Stack After Embedding a Stressor Material by Using a Liner App 20110266625 - Carter; Richard ; et al.	2011-11-03
Superior fill conditions in a replacement gate approach by corner rounding prior to completely removing a placeholder material Grant 8,048,792 - Beyer , et al. November 1, 2	2011-11-01
Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain Grant 8,039,335 - Beyer , et al. October 18, 2	2011-10-18
Structured strained substrate for forming strained transistors with reduced thickness of active layer Grant 8,030,148 - Hoentschel , et al. October 4, 2	2011-10-04
Strain Memorization In Strained Soi Substrates Of Semiconductor Devices App 20110210427 - Hoentschel; Jan ; et al.	2011-09-01
Transistors Comprising High-k Metal Gate Electrode Structures And Adapted Channel Semiconductor Materials App 20110210398 - Beyer; Sven ; et al.	2011-09-01
Contact Bars With Reduced Fringing Capacitance In A Semiconductor Device App 20110210380 - Scheiper; Thilo ; et al.	2011-09-01
Transistor Comprising a Buried High-K Metal Gate Electrode Structure App 20110210389 - Griebenow; Uwe ; et al.	2011-09-01
Field Effect Transistors For A Flash Memory Comprising A Self-aligned Charge Storage Region App 20110211394 - Scheiper; Thilo ; et al.	2011-09-01
Replacement Gate Approach Based On A Reverse Offset Spacer Applied Prior To Work Function Metal Deposition App 20110186915 - Scheiper; Thilo ; et al.	2011-08-04
Adjustment Of Transistor Characteristics Based On A Late Well Implantation App 20110186937 - Scheiper; Thilo ; et al.	2011-08-04
Enhanced Confinement Of Sensitive Materials Of A High-k Metal Gate Electrode Structure App 20110156099 - Hoentschel; Jan ; et al.	2011-06-30
High-k Metal Gate Electrode Structures Formed At Different Process Stages Of A Semiconductor Device App 20110156154 - Hoentschel; Jan ; et al.	2011-06-30
Predoped Semiconductor Material For A High-k Metal Gate Electrode Structure Of P- And N-channel Transistors App 20110156153 - Beyer; Sven ; et al.	2011-06-30
Transistor Including A High-k Metal Gate Electrode Structure Formed On The Basis Of A Simplified Spacer Regime App 20110129972 - Hoentschel; Jan ; et al.	2011-06-02
Performance Enhancement In Transistors Comprising High-k Metal Gate Stack By An Early Extension Implantation App 20110127617 - Scheiper; Thilo ; et al.	2011-06-02
Reducing The Series Resistance In Sophisticated Transistors By Embedding Metal Silicide Contact Regions Reliably Into Highly Doped Semiconductor Material App 20110127614 - Scheiper; Thilo ; et al.	2011-06-02
Work Function Adjustment In High-k Gate Stacks For Devices Of Different Threshold Voltage App 20110127616 - Hoentschel; Jan ; et al.	2011-06-02
High-k Metal Gate Electrode Structures Formed By Separate Removal Of Placeholder Materials Using A Masking Regime Prior To Gate Patterning App 20110127613 - Beyer; Sven ; et al.	2011-06-02
Performance Enhancement In Pfet Transistors Comprising High-k Metal Gate Stack By Increasing Dopant Confinement App 20110127618 - Scheiper; Thilo ; et al.	2011-06-02
Transistor including a high-K metal gate electrode structure formed prior to drain/source regions on the basis of a sacrificial carbon spacer Grant 7,943,462 - Beyer , et al. May 17, 2	2011-05-17
High-k Metal Gate Electrode Structures Formed By Separate Removal Of Placeholder Materials In Transistors Of Different Conductivity Type App 20110101470 - Hempel; Klaus ; et al.	2011-05-05
Semiconductor Device Comprising Nmos And Pmos Transistors With Embedded Si/ge Material For Creating Tensile And Compressive Strain App 20110104878 - Beyer; Sven ; et al.	2011-05-05
Strain Engineering In Three-dimensional Transistors Based On Globally Strained Semiconductor Base Layers App 20110101456 - Hoentschel; Jan ; et al.	2011-05-05
Transistor Including A High-k Metal Gate Electrode Structure Formed Prior To Drain/source Regions On The Basis Of A Superior Implantation Masking Effect App 20110101427 - Scheiper; Thilo ; et al.	2011-05-05
Transistor Including A High-k Metal Gate Electrode Structure Formed Prior To Drain/source Regions On The Basis Of A Sacrificial Carbon Spacer App 20110104863 - Beyer; Sven ; et al.	2011-05-05
Superior Fill Conditions In A Replacement Gate Approach By Corner Rounding Prior To Completely Removing A Placeholder Material App 20110073963 - Beyer; Sven ; et al.	2011-03-31
Optical Signal Transfer In A Semiconductor Device By Using Monolithic Opto-electronic Components App 20110073875 - Griebenow; Uwe ; et al.	2011-03-31
Maintaining Integrity Of A High-k Gate Stack By Passivation Using An Oxygen Plasma App 20110049585 - Beyer; Sven ; et al.	2011-03-03
Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain Grant 7,893,503 - Beyer , et al. February 22, 2	2011-02-22
Uniform High-k Metal Gate Stacks By Adjusting Threshold Voltage For Sophisticated Transistors By Diffusing A Metal Species Prior To Gate Patterning App 20100327373 - Carter; Richard ; et al.	2010-12-30
Enhanced Etch Stop Capability During Patterning Of Silicon Nitride Including Layer Stacks By Providing A Chemically Formed Oxide Layer During Semiconductor Processing App 20100304542 - Beyer; Sven ; et al.	2010-12-02
Adjusting Threshold Voltage For Sophisticated Transistors By Diffusing A Gate Dielectric Cap Layer Material Prior To Gate Dielectric Stabilization App 20100289089 - Carter; Richard ; et al.	2010-11-18
Threshold Adjustment Of Transistors Including High-k Metal Gate Electrode Structures Comprising An Intermediate Etch Stop Layer App 20100244141 - Beyer; Sven ; et al.	2010-09-30
Maintaining Integrity Of A High-k Gate Stack By An Offset Spacer Used To Determine An Offset Of A Strain-inducing Semiconductor Alloy App 20100244155 - Carter; Richard ; et al.	2010-09-30
Transistor having a locally provided metal silicide region in contact areas and a method of forming the transistor Grant 7,799,682 - Beyer , et al. September 21, 2	2010-09-21
Work Function Adjustment In A High-k Gate Electrode Structure After Transistor Fabrication By Using Lanthanum App 20100193872 - Carter; Richard ; et al.	2010-08-05
Short Channel Transistor With Reduced Length Variation By Using Amorphous Electrode Material During Implantation App 20100193860 - Scheiper; Thilo ; et al.	2010-08-05
Increased Depth Of Drain And Source Regions In Complementary Transistors By Forming A Deep Drain And Source Region Prior To A Cavity Etch App 20100193873 - Griebenow; Uwe ; et al.	2010-08-05
Semiconductor Device Comprising Nmos And Pmos Transistors With Embedded Si/ge Material For Creating Tensile And Compressive Strain App 20100187635 - BEYER; SVEN ; et al.	2010-07-29
Semiconductor device comprising NMOS and PMOS transistors with embedded Si/Ge material for creating tensile and compressive strain Grant 7,741,167 - Beyer , et al. June 22, 2	2010-06-22
Multiple Gate Transistor Having Homogenously Silicided Fin End Portions App 20100133614 - Beyer; Sven ; et al.	2010-06-03
Enhancing Integrity Of A High-k Gate Stack By Protecting A Liner At The Gate Bottom During Gate Head Exposure App 20100136762 - Beyer; Sven ; et al.	2010-06-03
Contacts And Vias Of A Semiconductor Device Formed By A Hard Mask And Double Exposure App 20100078823 - Beyer; Sven ; et al.	2010-04-01
Structured Strained Substrate For Forming Strained Transistors With Reduced Thickness Of Active Layer App 20100055867 - Hoentschel; Jan ; et al.	2010-03-04
Transistor Having A Strained Channel Region Caused By Hydrogen-induced Lattice Deformation App 20100025742 - Beyer; Sven ; et al.	2010-02-04
Field effect transistor and method of forming a field effect transistor Grant 7,629,211 - Beyer , et al. December 8, 2	2009-12-08
Semiconductor structure comprising field effect transistors with stressed channel regions and method of forming the same Grant 7,608,499 - Romero , et al. October 27, 2	2009-10-27
Two step optical planarizing layer etch Grant 7,601,641 - Geiss , et al. October 13, 2	2009-10-13
Two Step Optical Planarizing Layer Etch App 20090246959 - GEISS; Erik ; et al.	2009-10-01
Semiconductor Device Comprising Isolation Trenches Inducing Different Types Of Strain App 20090236667 - Schwan; Christoph ; et al.	2009-09-24
Semiconductor Device Comprising A Metal Gate Stack Of Reduced Height And Method Of Forming The Same App 20090218639 - Beyer; Sven ; et al.	2009-09-03
Method of making a semiconductor device comprising isolation trenches inducing different types of strain Grant 7,547,610 - Schwan , et al. June 16, 2	2009-06-16
Methods for fabricating an integrated circuit Grant 7,504,287 - Beyer , et al. March 17, 2	2009-03-17
Method For Forming A Deep Trench In An Soi Device By Reducing The Shielding Effect Of The Active Layer During The Deep Trench Etch Process App 20090032855 - Press; Patrick ; et al.	2009-02-05
Methods For Fabricating An Integrated Circuit App 20080233738 - BEYER; Sven ; et al.	2008-09-25
Semiconductor Device Comprising Nmos And Pmos Transistors With Embedded Si/ge Material For Creating Tensile And Compressive Strain App 20080099794 - Beyer; Sven ; et al.	2008-05-01
Semiconductor Device Comprising Isolation Trenches Inducing Different Types Of Strain App 20080079085 - Schwan; Christoph ; et al.	2008-04-03
Transistor Having A Locally Provided Metal Silicide Region In Contact Areas And A Method Of Forming The Transistor App 20080054371 - Beyer; Sven ; et al.	2008-03-06
Semiconductor Structure Comprising Field Effect Transistors With Stressed Channel Regions And Method Of Forming The Same App 20080023771 - Romero; Karla ; et al.	2008-01-31
Field Effect Transistor And Method Of Forming A Field Effect Transistor App 20080026531 - Beyer; Sven ; et al.	2008-01-31
Formation Of Silicided Surfaces For Silicon/carbon Source/drain Regions App 20070200176 - Kammler; Thorsten ; et al.	2007-08-30