Betz; Vaughn

Patent Applications and Registrations

Patent applications and USPTO patent grants for Betz; Vaughn.The latest application filed is for "method and apparatus for performing parallel routing using a multi-threaded routing procedure".

Company Profile

8.107.39

Betz; Vaughn - Toronto N/A CA
Betz; Vaughn - Ontario CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Characterization of power delivery network in field programmable gate arrays or digital integrated circuits Grant 11,018,668 - Zhao , et al. May 25, 2	2021-05-25
Method And Apparatus For Performing Parallel Routing Using A Multi-threaded Routing Procedure App 20210073453 - Betz; Vaughn ; et al.	2021-03-11
Method and apparatus for performing parallel routing using a multi-threaded routing procedure Grant 10,783,310 - Betz , et al. Sept	2020-09-22
Method and apparatus for deriving signal activities for power analysis and optimization Grant 10,417,362 - Neto , et al. Sept	2019-09-17
Characterization Of Power Delivery Network In Field Programmable Gate Arrays Or Digital Integrated Circuits App 20190165782 - ZHAO; Shuze ; et al.	2019-05-30
Method And Apparatus For Performing Parallel Routing Using A Multi-threaded Routing Procedure App 20190108303 - Betz; Vaughn ; et al.	2019-04-11
Method and apparatus for placing and routing partial reconfiguration modules Grant 10,242,146 - Goldman , et al.	2019-03-26
Method and apparatus for performing parallel routing using a multi-threaded routing procedure Grant 10,140,411 - Betz , et al. Nov	2018-11-27
Method and Apparatus for Implementing Soft Constraints in Tools Used for Designing Programmable Logic Devices App 20170337318 - Borer; Terry ; et al.	2017-11-23
Dynamic Parameter Operation Of An Fpga App 20170272073 - Betz; Vaughn ; et al.	2017-09-21
Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices Grant 9,754,065 - Borer , et al. September 5, 2	2017-09-05
Apparatus and associated methods for parallelizing clustering and placement Grant 9,594,859 - Padalia , et al. March 14, 2	2017-03-14
Method and Apparatus for Performing Parallel Routing Using a Multi-Threaded Routing Procedure App 20170068768 - Betz; Vaughn ; et al.	2017-03-09
Method and apparatus for performing parallel routing using a multi-threaded routing procedure Grant 9,536,034 - Betz , et al. January 3, 2	2017-01-03
Method and Apparatus for Placing and Routing Partial Reconfiguration Modules App 20160267212 - Goldman; David Samuel ; et al.	2016-09-15
Method and apparatus for utilizing constraints for the routing of a design on a programmable logic device Grant 9,443,054 - Betz , et al. September 13, 2	2016-09-13
Method and apparatus for placing and routing partial reconfiguration modules Grant 9,361,421 - Goldman , et al. June 7, 2	2016-06-07
Method and apparatus for protecting, optimizing, and reporting synchronizers Grant 9,342,640 - Fung , et al. May 17, 2	2016-05-17
PLD architecture for flexible placement of IP function blocks Grant 9,094,014 - Lee , et al. July 28, 2	2015-07-28
Method and Apparatus for Performing Parallel Routing Using a Multi-Threaded Routing Procedure App 20150154338 - Betz; Vaughn ; et al.	2015-06-04
Method and apparatus for performing parallel routing using a multi-threaded routing procedure Grant 8,935,650 - Betz , et al. January 13, 2	2015-01-13
Method and apparatus for deriving signal activities for power analysis and optimization Grant 8,898,603 - Neto , et al. November 25, 2	2014-11-25
Apparatus And Methods For Power Management In Integrated Circuits App 20140258956 - Lewis; David ; et al.	2014-09-11
Method and Apparatus for Performing Parallel Routing Using a Multi-Threaded Routing Procedure App 20140223403 - Betz; Vaughn ; et al.	2014-08-07
Pld Architecture For Flexible Placement Of Ip Function Blocks App 20140210515 - Lee; Andy L. ; et al.	2014-07-31
Method and apparatus for utilizing constraints for the routing of a design on a programmable logic device Grant 8,745,566 - Betz , et al. June 3, 2	2014-06-03
Method and apparatus for performing parallel routing using a multi-threaded routing procedure Grant 8,739,105 - Betz , et al. May 27, 2	2014-05-27
PLD architecture for flexible placement of IP function blocks Grant 8,732,646 - Lee , et al. May 20, 2	2014-05-20
Apparatus and methods for power management in integrated circuits Grant 8,732,635 - Lewis , et al. May 20, 2	2014-05-20
Method and apparatus for protecting, optimizing, and reporting synchronizers Grant 8,732,639 - Fung , et al. May 20, 2	2014-05-20
Method and apparatus for placement and routing of partial reconfiguration modules Grant 8,671,377 - Goldman , et al. March 11, 2	2014-03-11
Method and Apparatus for Implementing Soft Constraints in Tools Used for Designing Programmable Logic Devices App 20140047405 - Borer; Terry ; et al.	2014-02-13
Method and Apparatus for Performing Parallel Routing Using A Multi-Threaded Routing Procedure App 20130318491 - Betz; Vaughn ; et al.	2013-11-28
Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices Grant 8,589,849 - Borer , et al. November 19, 2	2013-11-19
Method and apparatus for performing path-level skew optimization and analysis for a logic design Grant 8,572,530 - Fung , et al. October 29, 2	2013-10-29
Method and apparatus for performing parallel routing using a multi-threaded routing procedure Grant 8,533,652 - Betz , et al. September 10, 2	2013-09-10
Systems and methods for optimizing placement and routing Grant 8,499,273 - Bozman , et al. July 30, 2	2013-07-30
Method and apparatus for implementing cross-talk based booster wires in a system on a field programmable gate array Grant 8,468,487 - Parpia , et al. June 18, 2	2013-06-18
Method and apparatus for utilizing constraints for the routing of a design on a programmable logic device Grant 8,443,325 - Betz , et al. May 14, 2	2013-05-14
Method and Apparatus For Performing Parallel Routing Using A Multi-Threaded Routing Procedure App 20130007689 - Betz; Vaughn ; et al.	2013-01-03
Method and apparatus for performing parallel routing using a multi-threaded routing procedure Grant 8,296,709 - Betz , et al. October 23, 2	2012-10-23
Flexible RAM clock enable Grant 8,271,821 - Yuan , et al. September 18, 2	2012-09-18
Method and Apparatus for Placement and Routing of Partial Reconfiguration Modules App 20120227026 - Goldman; David Samuel ; et al.	2012-09-06
Method and apparatus for deriving signal activities for power analysis and optimization Grant 8,250,500 - Neto , et al. August 21, 2	2012-08-21
Clock switch-over circuits and methods Grant 8,248,110 - Lai , et al. August 21, 2	2012-08-21
Methods and systems for improving a maximum operating frequency of an integrated circuit during a route phase Grant 8,191,028 - Bourgeault , et al. May 29, 2	2012-05-29
Method and Apparatus for Performing Parallel Routing Using a Multi-Threaded Routing Procedure App 20120131535 - Betz; Vaughn ; et al.	2012-05-24
Apparatus and Methods for Optimizing the Performance of Programmable Logic Devices App 20120089958 - Lewis; David ; et al.	2012-04-12
Method and apparatus for utilizing long-path and short-path timing constraints in an electronic-design-automation tool for routing Grant 8,156,463 - Fung , et al. April 10, 2	2012-04-10
Systems and methods for reducing static and total power consumption Grant 8,156,355 - Mendel , et al. April 10, 2	2012-04-10
Apparatus and methods for adjusting performance of integrated circuits Grant 8,138,786 - Lewis , et al. March 20, 2	2012-03-20
Error correction for programmable logic integrated circuits Grant 8,112,678 - Lewis , et al. February 7, 2	2012-02-07
Apparatus and methods for optimizing the performance of programmable logic devices using multiple supply voltage Grant 8,103,975 - Lewis , et al. January 24, 2	2012-01-24
Power-driven timing analysis and placement for programmable logic Grant 8,099,692 - Kretchmer , et al. January 17, 2	2012-01-17
Method and apparatus for performing parallel routing using a multi-threaded routing procedure Grant 8,095,906 - Betz , et al. January 10, 2	2012-01-10
Clock switch-over circuits and methods Grant 7,911,240 - Lai , et al. March 22, 2	2011-03-22
Power-aware RAM processing Grant 7,877,555 - Tessier , et al. January 25, 2	2011-01-25
Method and apparatus for deriving signal activities for power analysis and optimization Grant 7,877,710 - Neto , et al. January 25, 2	2011-01-25
Power-driven timing analysis and placement for programmable logic Grant 7,861,190 - Kretchmer , et al. December 28, 2	2010-12-28
Method and apparatus for performing path-level skew optimization and analysis for a logic design Grant 7,853,911 - Fung , et al. December 14, 2	2010-12-14
Method and apparatus for utilizing constraints for the routing of a design on a programmable logic device Grant 7,757,197 - Betz , et al. July 13, 2	2010-07-13
Method and apparatus for performing parallel routing using a multi-threaded routing procedure App 20100169858 - Betz; Vaughn ; et al.	2010-07-01
Periphery clock distribution network for a programmable logic device Grant 7,737,751 - Lai , et al. June 15, 2	2010-06-15
Optimizing long-path and short-path timing and accounting for manufacturing and operating condition variability Grant 7,725,853 - Fung , et al. May 25, 2	2010-05-25
Programmable logic device architectures and methods for implementing logic in those architectures Grant 7,716,623 - Vanderhoek , et al. May 11, 2	2010-05-11
Techniques for grouping circuit elements into logic blocks Grant 7,707,532 - Padalia , et al. April 27, 2	2010-04-27
Apparatus and Methods for Parallelizing Integrated Circuit Computer-Aided Design Software App 20100070979 - Ludwin; Adrian ; et al.	2010-03-18
Versatile logic element and logic array block Grant 7,671,626 - Lewis , et al. March 2, 2	2010-03-02
Efficient delay elements Grant 7,659,764 - Fung , et al. February 9, 2	2010-02-09
Distributed memory in field-programmable gate array integrated circuit devices Grant 7,656,191 - Lewis , et al. February 2, 2	2010-02-02
Efficient delay elements Grant 7,629,825 - Fung , et al. December 8, 2	2009-12-08
Apparatus and Methods for Adjusting Performance of Integrated Circuits App 20090289696 - Lewis; David ; et al.	2009-11-26
Programmable logic device architectures and methods for implementing logic in those architectures Grant 7,619,443 - Vanderhoek , et al. November 17, 2	2009-11-17
Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage Grant 7,594,208 - Borer , et al. September 22, 2	2009-09-22
Apparatus and methods for adjusting performance of integrated circuits Grant 7,573,317 - Lewis , et al. August 11, 2	2009-08-11
Computer-aided-design tools for reducing power consumption in programmable logic devices Grant 7,555,741 - Milton , et al. June 30, 2	2009-06-30
Systems And Methods For Reducing Static And Total Power Consumption App 20090138696 - Mendel; David ; et al.	2009-05-28
Systems and methods for reducing static and total power consumption in a programmable logic device Grant 7,467,314 - Mendel , et al. December 16, 2	2008-12-16
Method and apparatus for performing incremental compilation Grant 7,464,362 - Borer , et al. December 9, 2	2008-12-09
Apparatus And Methods For Power Management In Integrated Circuits App 20080263481 - Lewis; David ; et al.	2008-10-23
Apparatus And Methods For Optimizing The Performance Of Programmable Logic Devices App 20080263490 - Lewis; David ; et al.	2008-10-23
Methods for designing integrated circuits Grant 7,441,208 - Padalia , et al. October 21, 2	2008-10-21
Flexible RAM Clock Enable App 20080253220 - Yuan; Jinyong ; et al.	2008-10-16
Versatile logic element and logic array block Grant 7,432,734 - Lewis , et al. October 7, 2	2008-10-07
Distributed memory in field-programmable gate array integrated circuit devices App 20080231316 - Lewis; David ; et al.	2008-09-25
Automatic adjustment of optimization effort in configuring programmable devices Grant 7,415,682 - Padalia , et al. August 19, 2	2008-08-19
Method and apparatus for performing integrated global routing and buffer insertion Grant 7,412,680 - Gouterman , et al. August 12, 2	2008-08-12
Apparatus and methods for power management in integrated circuits Grant 7,405,589 - Lewis , et al. July 29, 2	2008-07-29
Apparatus and methods for optimizing the performance of programmable logic devices Grant 7,400,167 - Lewis , et al. July 15, 2	2008-07-15
Flexible RAM clock enable Grant 7,397,726 - Yuan , et al. July 8, 2	2008-07-08
Distributed memory in field-programmable gate array integrated circuit devices Grant 7,391,236 - Lewis , et al. June 24, 2	2008-06-24
Error correction for programmable logic integrated circuits Grant 7,328,377 - Lewis , et al. February 5, 2	2008-02-05
Method and apparatus for utilizing long-path and short-path timing constraints in an electronic-design-automation tool for routing Grant 7,308,664 - Fung , et al. December 11, 2	2007-12-11
Distributed random access memory in a programmable logic device Grant 7,304,499 - Lewis , et al. December 4, 2	2007-12-04
Versatile Logic Element And Logic Array Block App 20070252617 - Lewis; David M. ; et al.	2007-11-01
Optimizing long-path and short-path timing and accounting for manufacturing and operating condition variability Grant 7,290,232 - Fung , et al. October 30, 2	2007-10-30
Systems and methods for reducing static and total power consumption in programmable logic device architectures Grant 7,287,171 - Mendel , et al. October 23, 2	2007-10-23
Techniques for grouping circuit elements into logic blocks Grant 7,275,228 - Padalia , et al. September 25, 2	2007-09-25
Apparatus and methods for parallelizing integrated circuit computer-aided design software App 20070192766 - Padalia; Ketan ; et al.	2007-08-16
Optimizing long-path and short-path timing and accounting for manufacturing and operating condition variability Grant 7,254,789 - Fung , et al. August 7, 2	2007-08-07
Distributed memory in field-programmable gate array integrated circuit devices App 20070146178 - Lewis; David ; et al.	2007-06-28
Systems and methods for reducing static and total power consumption in a programmable logic device App 20070101175 - Mendel; David ; et al.	2007-05-03
Bypass-able carry chain in a programmable logic device Grant 7,205,791 - Lee , et al. April 17, 2	2007-04-17
Method and apparatus for utilizing long-path and short-path timing constraints in an electronic-design-automation tool Grant 7,207,020 - Fung , et al. April 17, 2	2007-04-17
Apparatus And Methods For Adjusting Performance Of Integrated Circuits App 20070069764 - Lewis; David ; et al.	2007-03-29
Method and apparatus for implementing soft constraints in tools used for designing systems on programmable logic devices Grant 7,194,720 - Borer , et al. March 20, 2	2007-03-20
Systems and methods for reducing static and total power consumption in a programmable logic device Grant 7,188,266 - Mendel , et al. March 6, 2	2007-03-06
Apparatus and methods for power management in integrated circuits App 20070040576 - Lewis; David ; et al.	2007-02-22
Apparatus and methods for optimizing the performance of programmable logic devices App 20070040577 - Lewis; David ; et al.	2007-02-22
Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage Grant 7,181,703 - Borer , et al. February 20, 2	2007-02-20
Variable delay circuitry Grant 7,138,844 - Lee , et al. November 21, 2	2006-11-21
Apparatus and methods for adjusting performance of integrated circuits Grant 7,129,745 - Lewis , et al. October 31, 2	2006-10-31
Automatic adjustment of optimization effort in configuring programmable devices App 20060225021 - Padalia; Ketan ; et al.	2006-10-05
Variable Delay Circuitry App 20060208785 - Lee; Andy L. ; et al.	2006-09-21
Distributed random access memory in a programmable logic device Grant 7,084,665 - Lewis , et al. August 1, 2	2006-08-01
Initializing a carry chain in a programmable logic device Grant 7,061,268 - Lee , et al. June 13, 2	2006-06-13
Automatic generation of programmable logic device architectures Grant 7,051,313 - Betz , et al. May 23, 2	2006-05-23
Apparatus and methods for adjusting performance of integrated circuits App 20050280437 - Lewis, David ; et al.	2005-12-22
Routing architecture for a programmable logic device Grant 6,970,014 - Lewis , et al. November 29, 2	2005-11-29
Techniques for identifying functional blocks in a design that match a template and combining the functional blocks into fewer programmable circuit elements Grant 6,957,412 - Betz , et al. October 18, 2	2005-10-18
Versatile logic element and logic array block Grant 6,937,064 - Lewis , et al. August 30, 2	2005-08-30
Versatile logic element and logic array block App 20050127944 - Lewis, David M. ; et al.	2005-06-16
System and method for optimizing routing lines in a programmable logic device Grant 6,895,570 - Lewis , et al. May 17, 2	2005-05-17
Heterogeneous interconnection architecture for programmable logic devices Grant 6,828,824 - Betz , et al. December 7, 2	2004-12-07
Flexible I/O routing resources Grant 6,826,741 - Johnson , et al. November 30, 2	2004-11-30
Heterogeneous interconnection architecture for programmable logic devices App 20040017222 - Betz, Vaughn ; et al.	2004-01-29
Routing architecture for a programmable logic device Grant 6,630,842 - Lewis , et al. October 7, 2	2003-10-07
Automatic generation of programmable logic device architectures Grant 6,631,510 - Betz , et al. October 7, 2	2003-10-07
Heterogeneous interconnection architecture for programmable logic devices Grant 6,590,419 - Betz , et al. July 8, 2	2003-07-08
System and method for asymmetric routing lines App 20020166106 - Lewis, David M. ; et al.	2002-11-07
Complementary architecture for field-programmable gate arrays Grant 5,537,341 - Rose , et al. July 16, 1	1996-07-16