Berzins; Matthew S.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Berzins; Matthew S..The latest application filed is for "integrated clock gater (icg) using clock cascode complimentary switch logic".

Company Profile

0.13.10

Berzins; Matthew S. - Cedar Park TX
Berzins; Matthew S. - Austin TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Integrated clock gater (ICG) using clock cascode complimentary switch logic Grant 9,450,578 - Berzins , et al. September 20, 2	2016-09-20
Integrated Clock Gater (icg) Using Clock Cascode Complimentary Switch Logic App 20160049930 - BERZINS; Matthew S. ; et al.	2016-02-18
Integrated clock gater (ICG) using clock cascode complimentary switch logic Grant 9,203,382 - Berzins , et al. December 1, 2	2015-12-01
Integrated Clock Gater (icg) Using Clock Cascode Complimentary Switch Logic App 20150145577 - BERZINS; Matthew S. ; et al.	2015-05-28
Integrated clock gater (ICG) using clock cascode complimentary switch logic Grant 8,975,949 - Berzins , et al. March 10, 2	2015-03-10
Integrated Clock Gater (icg) Using Clock Cascode Complimentary Switch Logic App 20140266396 - Berzins; Matthew S. ; et al.	2014-09-18
Pulsed state retention power gating flip-flop Grant 8,289,060 - Tower , et al. October 16, 2	2012-10-16
Linearized digital phase-locked loop method for maintaining end of packet time linearity Grant 7,826,581 - Prather , et al. November 2, 2	2010-11-02
Circuitry and method for buffering a power mode control signal Grant 7,683,697 - Berzins , et al. March 23, 2	2010-03-23
Circuitry And Method For Buffering A Power Mode Control Signal App 20090295467 - Berzins; Matthew S. ; et al.	2009-12-03
Flip-flop having logic state retention during a power down mode and method therefor Grant 7,583,121 - Berzins , et al. September 1, 2	2009-09-01
Flip-flop Having Logic State Retention During A Power Down Mode And Method Therefor App 20090058485 - Berzins; Matthew S. ; et al.	2009-03-05
Pulsed State Retention Power Gating Flip-flop App 20080315932 - Tower; Samuel J. ; et al.	2008-12-25
Circuit and method for CMOS voltage level translation Grant 7,239,178 - Cornell , et al. July 3, 2	2007-07-03
Low duty cycle distortion differential to CMOS translator Grant 7,176,720 - Prather , et al. February 13, 2	2007-02-13
Method and circuit for translating a differential signal to complementary CMOS levels Grant 7,173,453 - Prather , et al. February 6, 2	2007-02-06
Method and circuit for translating a differential signal to complmentary CMOS levels App 20050134314 - Prather, Stephen M. ; et al.	2005-06-23
Method and apparatus for differential signal detection Grant 6,781,465 - Berzins , et al. August 24, 2	2004-08-24

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