| Patent | Date |
|---|
Method for reducing power consumption in scannable flip-flops without additional circuitry
Grant 11,092,649 - Berzins August 17, 2 | 2021-08-17 |
Low-power low-setup integrated clock gating cell with complex enable selection
Grant 10,819,342 - Berzins , et al. October 27, 2 | 2020-10-27 |
Low power integrated clock gating system and method
Grant 10,784,864 - Berzins , et al. Sept | 2020-09-22 |
Power rail for standard cell block
Grant 10,784,198 - Sengupta , et al. Sept | 2020-09-22 |
Low Power Integrated Clock Gating System And Method
App 20200295758 - BERZINS; Matthew ; et al. | 2020-09-17 |
Novel Method For Reducing Power Consumption In Scannable Flip-flops Without Additional Circuitry
App 20200292617 - BERZINS; Matthew | 2020-09-17 |
Power grid and standard cell co-design structure and methods thereof
Grant 10,748,889 - Berzins , et al. A | 2020-08-18 |
System and method for improving scan hold-time violation and low voltage operation in sequential circuit
Grant 10,720,204 - Berzins | 2020-07-21 |
Low-power Low-setup Integrated Clock Gating Cell With Complex Enable Selection
App 20200204180 - BERZINS; Matthew ; et al. | 2020-06-25 |
Layout connection isolation technique for improving immunity to jitter and voltage drop in a standard cell
Grant 10,607,982 - Berzins , et al. | 2020-03-31 |
High speed domino-based flip flop
Grant 10,581,410 - Berzins , et al. | 2020-03-03 |
Layout Connection Isolation Technique For Improving Immunity To Jitter And Voltage Drop In A Standard Cell
App 20200020678 - BERZINS; Matthew ; et al. | 2020-01-16 |
Power Grid And Standard Cell Co-design Structure And Methods Thereof
App 20190385999 - BERZINS; Matthew ; et al. | 2019-12-19 |
Dynamic flip flop having data independent P-stack feedback
Grant 10,382,017 - Berzins , et al. A | 2019-08-13 |
System And Method For Improving Scan Hold-time Violation And Low Voltage Operation In Sequential Circuit
App 20190221255 - BERZINS; Matthew | 2019-07-18 |
Multi-bit flip-flops
Grant 10,353,000 - Yoon , et al. July 16, 2 | 2019-07-16 |
Low power integrated clock gating cell using controlled inverted clock
Grant 10,298,235 - Lim , et al. | 2019-05-21 |
System and method for improving scan hold-time violation and low voltage operation in sequential circuit
Grant 10,262,723 - Berzins | 2019-04-16 |
System And Method For Improving Scan Hold-time Violation And Low Voltage Operation In Sequential Circuit
App 20180342287 - BERZINS; Matthew | 2018-11-29 |
System And Method For Reducing Power Consumption In Scannable Circuit
App 20180340979 - BERZINS; Matthew | 2018-11-29 |
Low Power Integrated Clock Gating Cell Using Controlled Inverted Clock
App 20180287610 - LIM; James Jung ; et al. | 2018-10-04 |
Power Rail For Standard Cell Block
App 20180269152 - Sengupta; Rwik ; et al. | 2018-09-20 |
Using deep sub-micron stress effects and proximity effects to create a high performance standard cell
Grant 9,904,758 - Berzins , et al. February 27, 2 | 2018-02-27 |
Semiconductor circuit including flip-flop
Grant 9,899,990 - Kim , et al. February 20, 2 | 2018-02-20 |
Multi-bit flip-flops and scan chain circuits
Grant 9,891,283 - Kim , et al. February 13, 2 | 2018-02-13 |
Using Deep Sub-micron Stress Effects And Proximity Effects To Create A High Performance Standard Cell
App 20170337320 - BERZINS; Matthew ; et al. | 2017-11-23 |
Flip-flop with zero-delay bypass mux
Grant 9,793,881 - Wells , et al. October 17, 2 | 2017-10-17 |
Multi-bit Flip-flops
App 20170292993 - YOON; DOO-SEOK ; et al. | 2017-10-12 |
Low power minimal disruptive method to implement large quantity push and pull useful-skew schedules with enabling circuits in a clock-mesh based design
Grant 9,779,201 - Millar , et al. October 3, 2 | 2017-10-03 |
Low power integrated clock gating cell with internal control signal
Grant 9,768,756 - Lim , et al. September 19, 2 | 2017-09-19 |
Low Power Integrated Clock Gating Cell With Internal Control Signal
App 20170201241 - LIM; James Jung ; et al. | 2017-07-13 |
High Speed Domino-based Flip Flop
App 20170077908 - BERZINS; Matthew ; et al. | 2017-03-16 |
Semiconductor Circuit Including Flip-flop
App 20170070214 - KIM; SAN-HA ; et al. | 2017-03-09 |
Apparatus for low power high speed integrated clock gating cell
Grant 9,564,897 - Berzins , et al. February 7, 2 | 2017-02-07 |
Multi-bit Flip-flops And Scan Chain Circuits
App 20170016955 - KIM; MIN-SU ; et al. | 2017-01-19 |
Multi-bit flip-flops and scan chain circuits
Grant 9,473,117 - Kim , et al. October 18, 2 | 2016-10-18 |
Multi-bit Flip-flops And Scan Chain Circuits
App 20160241219 - KIM; Min-Su ; et al. | 2016-08-18 |
Low power toggle latch-based flip-flop including integrated clock gating logic
Grant 9,419,590 - Berzins , et al. August 16, 2 | 2016-08-16 |
Novel Low Power Minimal Disruptive Method To Implement Large Quantity Push & Pull Useful-skew Schedules With Enabling Circuits In A Clock-mesh Based Design
App 20160117434 - MILLAR; Brian ; et al. | 2016-04-28 |
Low Power Toggle Latch-based Flip-flop Including Integrated Clock Gating Logic
App 20150200652 - BERZINS; Matthew ; et al. | 2015-07-16 |
Circuit and method for rapid power up of a differential output driver
Grant 7,394,293 - Waldrip , et al. July 1, 2 | 2008-07-01 |
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