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name:-0.013875007629395
name:-0.048437118530273
name:-0.00052404403686523
Bertin; Claude Louis Patent Filings

Bertin; Claude Louis

Patent Applications and Registrations

Patent applications and USPTO patent grants for Bertin; Claude Louis.The latest application filed is for "intrinsic dual gate oxide mosfet using a damascene gate process".

Company Profile
0.40.7
  • Bertin; Claude Louis - South Burlington VT
  • Bertin; Claude Louis - S. Burlington VT
  • Bertin; Claude Louis - Burlington VT
  • Bertin; Claude Louis - So. Burlington VT
  • Bertin; Claude Louis - South Berlington VT
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Intrinsic dual gate oxide MOSFET using a damascene gate process
Grant 7,276,775 - Bertin , et al. October 2, 2
2007-10-02
Coaxial wiring within SOI semiconductor, PCB to system for high speed operation and signal quality
Grant 6,943,452 - Bertin , et al. September 13, 2
2005-09-13
Intrinsic dual gate oxide mosfet using a damascene gate process
App 20030109090 - Bertin, Claude Louis ;   et al.
2003-06-12
Intrinsic dual gate oxide MOSFET using a damascene gate process
Grant 6,531,410 - Bertin , et al. March 11, 2
2003-03-11
System and method for improving dram single cell fail fixability and flexibility repair at module level and universal laser fuse/anti-fuse latch therefor
App 20020196693 - Bertin, Claude Louis ;   et al.
2002-12-26
Micro-flex technology in semiconductor packages
Grant 6,444,490 - Bertin , et al. September 3, 2
2002-09-03
Intrinsic dual gate oxide MOSFET using a damascene gate process
App 20020119637 - Bertin, Claude Louis ;   et al.
2002-08-29
Coaxial wiring within SOI semiconductor, PCB to system for high speed operation and signal quality
App 20020101723 - Bertin, Claude Louis ;   et al.
2002-08-01
Through-chip conductors for low inductance chip-to-chip integration and off-chip connections
Grant 6,410,431 - Bertin , et al. June 25, 2
2002-06-25
Coaxial wiring within SOI semiconductor, PCB to system for high speed operation and signal quality
Grant 6,388,198 - Bertin , et al. May 14, 2
2002-05-14
Decode scheme for programming antifuses arranged in banks
Grant 6,339,559 - Bertin , et al. January 15, 2
2002-01-15
Micro-flex technology in semiconductor packages
App 20010039074 - Bertin, Claude Louis ;   et al.
2001-11-08
Micro-flex technology in semiconductor packages
App 20010035529 - Bertin, Claude Louis ;   et al.
2001-11-01
Micro-flex technology in semiconductor packages
Grant 6,300,687 - Bertin , et al. October 9, 2
2001-10-09
Highly integrated chip-on-chip packaging
Grant 6,294,406 - Bertin , et al. September 25, 2
2001-09-25
Impedance control using fuses
Grant 6,243,283 - Bertin , et al. June 5, 2
2001-06-05
Switched body SOI (silicon on insulator) circuits and fabrication method therefor
Grant 6,239,649 - Bertin , et al. May 29, 2
2001-05-29
Through-chip conductors for low inductance chip-to-chip integration and off-chip connections
App 20010001292 - Bertin, Claude Louis ;   et al.
2001-05-17
Through-chip conductors for low inductance chip-to-chip integration and off-chip connections
Grant 6,222,276 - Bertin , et al. April 24, 2
2001-04-24
Impedance control using fuses
Grant 6,141,245 - Bertin , et al. October 31, 2
2000-10-31
Highly integrated chip-on-chip packaging
Grant 5,977,640 - Bertin , et al. November 2, 1
1999-11-02
Machine structures fabricated of multiple microstructure layers
Grant 5,955,818 - Bertin , et al. September 21, 1
1999-09-21
Microconnectors
Grant 5,956,575 - Bertin , et al. September 21, 1
1999-09-21
Semiconductor stack structures and fabrication/sparing methods utilizing programmable spare circuit
Grant 5,946,545 - Bertin , et al. August 31, 1
1999-08-31
Multichip semiconductor structures with consolidated circuitry and programmable ESD protection for input/output nodes
Grant 5,943,254 - Bakeman, Jr. , et al. August 24, 1
1999-08-24
Methods and apparatus for burn-in stressing and simultaneous testing of semiconductor device chips in a multichip module
Grant 5,923,181 - Beilstein, Jr. , et al. July 13, 1
1999-07-13
Three device BICMOS gain cell
Grant 5,909,400 - Bertin , et al. June 1, 1
1999-06-01
Multi-view imaging apparatus
Grant 5,907,178 - Baker , et al. May 25, 1
1999-05-25
Microconnectors
Grant 5,903,059 - Bertin , et al. May 11, 1
1999-05-11
Reference potential for sensing data in electronic storage element
Grant 5,880,988 - Bertin , et al. March 9, 1
1999-03-09
Packaged electronic module and integral sensor array
Grant 5,869,896 - Baker , et al. February 9, 1
1999-02-09
Chip function separation onto separate stacked chips
Grant 5,818,748 - Bertin , et al. October 6, 1
1998-10-06
Integrated high-performance decoupling capacitor
Grant 5,811,868 - Bertin , et al. September 22, 1
1998-09-22
Methods for fabricating multichip semiconductor structures with consolidated circuitry and programmable ESD protection for input/output nodes
Grant 5,807,791 - Bertin , et al. September 15, 1
1998-09-15
Semiconductor stack structures and fabrication sparing methods utilizing programmable spare circuit
Grant 5,798,282 - Bertin , et al. August 25, 1
1998-08-25
Method and workpiece for connecting a thin layer to a monolithic electronic modules surface and associated module packaging
Grant 5,786,628 - Beilstein, Jr. , et al. July 28, 1
1998-07-28
Programmable logic array
Grant 5,781,031 - Bertin , et al. July 14, 1
1998-07-14
Electronic modules with integral sensor arrays
Grant 5,763,943 - Baker , et al. June 9, 1
1998-06-09
Method of making a machine structures fabricated of mutiple microstructure layers
Grant 5,763,318 - Bertin , et al. June 9, 1
1998-06-09
Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging
Grant 5,719,438 - Beilstein, Jr. , et al. February 17, 1
1998-02-17
Process for controlling distance between integrated circuit chips in an electronic module
Grant 5,712,190 - Bertin , et al. January 27, 1
1998-01-27
Integrated mulitchip memory module, structure and fabrication
Grant 5,702,984 - Bertin , et al. December 30, 1
1997-12-30
Methods and apparatus for burn-in stressing and simultaneous testing of semiconductor device chips in a multichip module
Grant 5,686,843 - Beilstein, Jr. , et al. November 11, 1
1997-11-11
Three-dimensional SRAM trench structure and fabrication method therefor
Grant 5,670,803 - Beilstein, Jr. , et al. September 23, 1
1997-09-23
Process for forming a polysilicon electrode in a trench
Grant 5,656,544 - Bergendahl , et al. August 12, 1
1997-08-12
Endcap chip with conductive, monolithic L-connect for multichip stack
Grant 5,648,684 - Bertin , et al. July 15, 1
1997-07-15
Semiconductor chip having chip metal layer and transfer metal layer composed of same metal, and corresponding electronic module
Grant 5,644,162 - Beilstein, Jr. , et al. July 1, 1
1997-07-01

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