Berthelon; Remy

Patent Applications and Registrations

Patent applications and USPTO patent grants for Berthelon; Remy.The latest application filed is for "strained transistors and phase change memory".

Company Profile

8.8.10

Berthelon; Remy - Saint Martin Heres FR
BERTHELON; Remy - Saint Martin d'Heres FR
Berthelon; Remy - Grenoble FR
Berthelon; Remy - Grenoble Cedex FR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Phase-change memory with insulated walls Grant 11,411,177 - Boivin , et al. August 9, 2	2022-08-09
Strained Transistors And Phase Change Memory App 20210343788 - BERTHELON; Remy ; et al.	2021-11-04
Electronic Chip With Two Phase Change Memories App 20210305502 - BERTHELON; Remy ; et al.	2021-09-30
Phase-change Memory App 20200381617 - BOIVIN; Philippe ; et al.	2020-12-03
Integrated circuit chip with strained NMOS and PMOS transistors Grant 10,777,680 - Berthelon , et al. Sept	2020-09-15
3D SRAM circuit with double gate transistors with improved layout Grant 10,741,565 - Andrieu , et al. A	2020-08-11
Optimized double-gate transistors and fabricating process Grant 10,546,929 - Andrieu , et al. Ja	2020-01-28
Integrated circuit comprising balanced cells at the active Grant 10,504,897 - Andrieu , et al. Dec	2019-12-10
Integrated Circuit Chip With Strained Nmos And Pmos Transistors App 20190363190 - BERTHELON; Remy ; et al.	2019-11-28
Integrated circuit including balanced cells limiting an active area Grant 10,446,548 - Andrieu , et al. Oc	2019-10-15
3d Sram Circuit With Double Gate Transistors With Improved Layout App 20190312039 - Andrieu; Francois ; et al.	2019-10-10
Integrated circuit chip with strained NMOS and PMOS transistors Grant 10,418,486 - Berthelon , et al. Sept	2019-09-17
Method of forming strained MOS transistors Grant 10,263,110 - Berthelon , et al.	2019-04-16
Transistors Double Grilles Optimises Et Procede De Fabrication App 20190027560 - ANDRIEU; Francois ; et al.	2019-01-24
Integrated Circuit Chip With Strained Nmos And Pmos Transistors App 20180331221 - BERTHELON; Remy ; et al.	2018-11-15
Integrated Circuit Including Balanced Cells Limiting An Active Area App 20180083006 - ANDRIEU; Francois ; et al.	2018-03-22
Integrated Circuit Including Balanced Cells Limiting An Active Area App 20180083005 - ANDRIEU; Francois ; et al.	2018-03-22
Method Of Forming Strained Mos Transistors App 20170194498 - Berthelon; Remy ; et al.	2017-07-06

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