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Patent applications and USPTO patent grants for BERGER; DANIEL GEORGE.The latest application filed is for "stacked semiconductor devices having dissimilar-sized dies".
Patent | Date |
---|---|
Stacked Semiconductor Devices Having Dissimilar-sized Dies App 20200365481 - ENGLAND; LUKE ;   et al. | 2020-11-19 |
Stacked semiconductor devices having dissimilar-sized dies Grant 10,818,570 - England , et al. October 27, 2 | 2020-10-27 |
Conductive adhesive composition Grant 7,405,247 - Sachdev , et al. July 29, 2 | 2008-07-29 |
Conductive adhesive rework method Grant 7,393,419 - Sachdev , et al. July 1, 2 | 2008-07-01 |
Conductive Adhesive Rework Method App 20080017223 - Sachdev; Krishna G. ;   et al. | 2008-01-24 |
Thermal interface adhesive and rework Grant 7,312,261 - Sachdev , et al. December 25, 2 | 2007-12-25 |
Conductive Adhesive Composition App 20070270536 - Sachdev; Krishna G. ;   et al. | 2007-11-22 |
Temporary chip attach method using reworkable conductive adhesive interconnections App 20060014309 - Sachdev; Krishna Gandhi ;   et al. | 2006-01-19 |
Thermal Interface Adhesive And Rework App 20050256241 - Sachdev, Krishna G. ;   et al. | 2005-11-17 |
Polymer and ceramic composite electronic substrates Grant 6,528,145 - Berger , et al. March 4, 2 | 2003-03-04 |
Method for building interconnect structures by injection molded solder and structures built Grant 6,133,633 - Berger , et al. October 17, 2 | 2000-10-17 |
Interconnect for low temperature chip attachment Grant 6,127,735 - Berger , et al. October 3, 2 | 2000-10-03 |
Wafer test and burn-in platform using ceramic tile supports Grant 6,020,750 - Berger , et al. February 1, 2 | 2000-02-01 |
Method for building interconnect structures by injection molded solder and structures built Grant 5,775,569 - Berger , et al. July 7, 1 | 1998-07-07 |
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