Bergendahl; Jason R.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Bergendahl; Jason R..The latest application filed is for "fpga specialist processing block for machine learning".
- Bergendahl; Jason R. - Cupertino CA
- Bergendahl; Jason R. - San Jose CA
- Bergendahl; Jason R. - Sunnyvale CA
- Bergendahl; Jason R. - San Mateo CA
- Bergendahl; Jason R. - Campbell CA
| Patent | Date |
|---|---|
| FPGA Specialist Processing Block for Machine Learning App 20210182022 - Langhammer; Martin ; et al. | 2021-06-17 |
| FPGA Specialist Processing Block for Machine Learning App 20210182023 - Langhammer; Martin ; et al. | 2021-06-17 |
| FPGA Specialist Processing Block for Machine Learning App 20200327271 - Langhammer; Martin ; et al. | 2020-10-15 |
| Circuit for and method of providing a programmable connector of an integrated circuit device Grant 10,528,513 - Chan , et al. J | 2020-01-07 |
| Regional signal-distribution network for an integrated circuit Grant 7,617,472 - Bergendahl , et al. November 10, 2 | 2009-11-10 |
| Reversible input/output delay line for bidirectional input/output blocks Grant 7,589,557 - Bergendahl , et al. September 15, 2 | 2009-09-15 |
| Data alignment and deskewing module Grant 7,551,646 - Zhang , et al. June 23, 2 | 2009-06-23 |
| Bimodal source synchronous interface Grant 7,502,433 - Sasaki , et al. March 10, 2 | 2009-03-10 |
| Method and apparatus for a programmable level translator Grant 7,456,654 - Rau , et al. November 25, 2 | 2008-11-25 |
| Regional signal-distribution network for an integrated circuit Grant 7,353,487 - Bergendahl , et al. April 1, 2 | 2008-04-01 |
| Clock signal-distribution network for an integrated circuit Grant 7,145,362 - Bergendahl , et al. December 5, 2 | 2006-12-05 |
| Multi-purpose source synchronous interface circuitry Grant 7,091,890 - Sasaki , et al. August 15, 2 | 2006-08-15 |
| Bimodal serial to parallel converter with bitslip controller Grant 6,985,096 - Sasaki , et al. January 10, 2 | 2006-01-10 |
| Windowing circuit for aligning data and clock signals Grant 6,864,715 - Bauer , et al. March 8, 2 | 2005-03-08 |
| Methods for aligning data and clock signals Grant 6,798,241 - Bauer , et al. September 28, 2 | 2004-09-28 |
| Low pass filter Grant 6,559,715 - Frake , et al. May 6, 2 | 2003-05-06 |
| Digitally controlled impedance for I/O of an integrated circuit device Grant 6,489,837 - Schultz , et al. December 3, 2 | 2002-12-03 |
| Digitally controlled impedance for I/O of an integrated circuit device Grant 6,445,245 - Schultz , et al. September 3, 2 | 2002-09-03 |
| Digitally controlled impedance for I/O of an integrated circuit device App 20020101278 - Schultz, David P. ; et al. | 2002-08-01 |
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