| Patent | Date |
|---|
Wafer Bonded Piezoresistive And Piezoelectric Force Sensor And Related Methods Of Manufacture
App 20220260435 - BERGEMONT; Albert ; et al. | 2022-08-18 |
Wafer bonded piezoresistive and piezoelectric force sensor and related methods of manufacture
Grant 11,243,126 - Bergemont , et al. February 8, 2 | 2022-02-08 |
Wafer Bonded Piezoresistive And Piezoelectric Force Sensor And Related Methods Of Manufacture
App 20200378845 - BERGEMONT; Albert ; et al. | 2020-12-03 |
Integrated Systems With Force Or Strain Sensing And Haptic Feedback
App 20200278748 - TSAI; Julius Minglin ; et al. | 2020-09-03 |
Vertical semiconductor device having frontside interconnections
Grant 9,673,316 - Blair , et al. June 6, 2 | 2017-06-06 |
EEPROM memory cell with a coupler region and method of making the same
Grant 9,450,052 - Bergemont , et al. September 20, 2 | 2016-09-20 |
Methods of forming coaxial feedthroughs for 3D integrated circuits
Grant 9,184,113 - Sridhar , et al. November 10, 2 | 2015-11-10 |
Dynamic trim method for non volatile memory products
Grant 9,129,710 - He , et al. September 8, 2 | 2015-09-08 |
N-channel multi-time programmable memory devices
Grant 8,975,685 - He , et al. March 10, 2 | 2015-03-10 |
Low-noise, high-gain semiconductor device incorporating BCD (Bipolar-CMOS-DMOS) technology and process of making the same
Grant 8,951,856 - Lu , et al. February 10, 2 | 2015-02-10 |
Methods of forming coaxial feedthroughs for 3D integrated circuits
Grant 8,940,631 - Sridhar , et al. January 27, 2 | 2015-01-27 |
Inductors and methods for integrated circuits
Grant 8,847,365 - Ellul , et al. September 30, 2 | 2014-09-30 |
Low-noise, high-gain semiconductor device incorporating BCD (bipolar-CMOS-DMOS) technology
Grant 8,796,767 - Lu , et al. August 5, 2 | 2014-08-05 |
3D chip package with shielded structures
Grant 8,686,543 - Bergemont , et al. April 1, 2 | 2014-04-01 |
N-Channel Multi-Time Programmable Memory Devices
App 20140063958 - He; Yi ; et al. | 2014-03-06 |
Dynamic trim method for non-volatile memory products
Grant 8,630,137 - He , et al. January 14, 2 | 2014-01-14 |
3d Chip Package With Shielded Structures
App 20130105950 - Bergemont; Albert ; et al. | 2013-05-02 |
Light sensor using wafer-level packaging
Grant 8,405,115 - Samoilov , et al. March 26, 2 | 2013-03-26 |
Inductors and Methods for Integrated Circuits
App 20130071983 - Ellul; Joseph P. ; et al. | 2013-03-21 |
Inductors having inductor axis parallel to substrate surface
Grant 8,344,478 - Ellul , et al. January 1, 2 | 2013-01-01 |
Minimum cost method for forming high density passive capacitors for replacement of discrete board capacitors using a minimum cost 3D wafer-to-wafer modular integration scheme
Grant 7,943,473 - Ellul , et al. May 17, 2 | 2011-05-17 |
Multi-programmable non-volatile memory cell
Grant 7,944,750 - Bergemont , et al. May 17, 2 | 2011-05-17 |
Inductors and Methods for Integrated Circuits
App 20110095395 - Ellul; Joseph P. ; et al. | 2011-04-28 |
Light Sensor Using Wafer-Level Packaging
App 20100187557 - Samoilov; Arkadii V. ; et al. | 2010-07-29 |
Minimum Cost Method for Forming High Density Passive Capacitors for Replacement of Discrete Board Capacitors Using a Minimum Cost 3D Wafer-to-Wafer Modular Integration Scheme
App 20100178747 - Ellul; Joseph Paul ; et al. | 2010-07-15 |
Common source EEPROM and flash memory
Grant RE40,976 - Bergemont , et al. November 17, 2 | 2009-11-17 |
One or multiple-times programmable device
Grant 7,535,758 - Bergemont , et al. May 19, 2 | 2009-05-19 |
One or multiple-times programmable device
App 20080186773 - Bergemont; Albert ; et al. | 2008-08-07 |
Low power high density random access memory flash cells and arrays
Grant 7,324,387 - Bergemont , et al. January 29, 2 | 2008-01-29 |
Single poly EPROM cell having smaller size and improved data retention compatible with advanced CMOS process
Grant 6,905,929 - Merrill , et al. June 14, 2 | 2005-06-14 |
Method of forming an isolation structure for an integrated circuit utilizing grown and deposited oxide
Grant 6,830,988 - Bergemont December 14, 2 | 2004-12-14 |
Common source EEPROM and flash memory
Grant 6,606,265 - Bergemont , et al. August 12, 2 | 2003-08-12 |
EEPROM memory cell array embedded on core CMOS
Grant 6,563,731 - Bergemont May 13, 2 | 2003-05-13 |
Extended drain MOSFET for programming an integrated fuse element to high resistance in low voltage process technology
Grant 6,525,397 - Kalnitsky , et al. February 25, 2 | 2003-02-25 |
EEPROM memory cell embedded on core CMOS for analog applications
Grant 6,507,516 - Bergemont January 14, 2 | 2003-01-14 |
Common source EEPROM and flash memory
App 20020176286 - Bergemont, Albert ; et al. | 2002-11-28 |
Methods of fabricating floating gate semiconductor device with reduced erase voltage
Grant 6,368,917 - Kalnitsky , et al. April 9, 2 | 2002-04-09 |
Dielectric-based anti-fuse cell with polysilicon contact plug and method for its manufacture
Grant 6,362,023 - Bergemont , et al. March 26, 2 | 2002-03-26 |
Method for forming a non-volatile memory cell that eliminates substrate trenching
Grant 6,362,050 - Kalnitsky , et al. March 26, 2 | 2002-03-26 |
EPROM and flash memory cells with source-side injection and a gate dielectric that traps hot electrons during programming
Grant 6,327,187 - Bergemont , et al. December 4, 2 | 2001-12-04 |
Single-poly EPROM cell with CMOS compatible programming voltages
Grant 6,271,560 - Kalnitsky , et al. August 7, 2 | 2001-08-07 |
Dielectric-based anti-fuse cell with polysilicon contact plug and method for its manufacture
Grant 6,249,010 - Bergemont , et al. June 19, 2 | 2001-06-19 |
Floating gate semiconductor device with reduced erase voltage
Grant 6,236,082 - Kalnitsky , et al. May 22, 2 | 2001-05-22 |
Method for forming a non-volatile memory cell that eliminates substrate trenching
App 20010000626 - Kalnitsky, Alexander ; et al. | 2001-05-03 |
Schottky diode with reduced size
Grant 6,218,688 - Kalnitsky , et al. April 17, 2 | 2001-04-17 |
EPROM and flash memory cells with source-side injection and a gate dielectric that traps hot electrons during programming
Grant 6,208,557 - Bergemont , et al. March 27, 2 | 2001-03-27 |
I/O circuit that utilizes a pair of well structures as resistors to delay an ESD event and as diodes for ESD protection
Grant 6,184,557 - Poplevine , et al. February 6, 2 | 2001-02-06 |
Method of fabricating a high density EEPROM array
Grant 6,177,315 - Bergemont , et al. January 23, 2 | 2001-01-23 |
Erasable frohmann-bentchkowsky memory transistor that stores multiple bits of data
Grant 6,157,574 - Kalnitsky , et al. December 5, 2 | 2000-12-05 |
Memory array having Frohmann-Bentchkowsky EPROM cells with a reduced number of access transistors
Grant 6,137,722 - Kalnitsky , et al. October 24, 2 | 2000-10-24 |
Memory device having erasable Frohmann-Bentchkowsky EPROM cells that use a well-to-floating gate coupled voltage during erasure
Grant 6,137,723 - Bergemont , et al. October 24, 2 | 2000-10-24 |
Memory cell having an erasable Frohmann-Bentchkowsky memory transistor
Grant 6,130,840 - Bergemont , et al. October 10, 2 | 2000-10-10 |
Sense amplifier having a bias circuit with a reduced size
Grant 6,122,204 - Poplevine , et al. September 19, 2 | 2000-09-19 |
High voltage split gate CMOS transistors built in standard 2-poly core CMOS
Grant 6,118,157 - Bergemont September 12, 2 | 2000-09-12 |
Process for fabricating trench isolation structure for integrated circuits
Grant 6,110,797 - Perry , et al. August 29, 2 | 2000-08-29 |
Method for forming a semiconductor device having non-volatile memory cells, High-voltage transistors, and low-voltage, deep sub-micron transistors
Grant 6,087,211 - Kalnitsky , et al. July 11, 2 | 2000-07-11 |
Method for forming a bipolar-based active pixel sensor cell with metal contact and increased capacitive coupling to the base region
Grant 6,080,601 - Bergemont , et al. June 27, 2 | 2000-06-27 |
Substrate biasing circuit that utilizes a gated diode to set the bias on the substrate
Grant 6,078,211 - Kalnitsky , et al. June 20, 2 | 2000-06-20 |
Single-poly EPROM cell with CMOS compatible programming voltages
Grant 6,055,185 - Kalnitsky , et al. April 25, 2 | 2000-04-25 |
Antifuse with a silicide layer overlying a diffusion region
Grant 6,031,275 - Kalnitsky , et al. February 29, 2 | 2000-02-29 |
Neural network active pixel cell
Grant 6,011,295 - Merrill , et al. January 4, 2 | 2000-01-04 |
EPROM and flash memory cells with source-side injection
Grant 5,982,669 - Kalnitsky , et al. November 9, 1 | 1999-11-09 |
Single-poly EEPROM cell that is programmable and erasable in a low-voltage environment
Grant 5,940,324 - Chi , et al. August 17, 1 | 1999-08-17 |
Method for forming a mixed-signal CMOS circuit that includes non-volatile memory cells
Grant 5,908,311 - Chi , et al. June 1, 1 | 1999-06-01 |
MOS-based active pixel sensor cell that utilizes the parasitic bipolar action of the cell to output image data
Grant 5,847,422 - Chi , et al. December 8, 1 | 1998-12-08 |
Self-convergent method for programming FLASH and EEPROM memory cells that moves the threshold voltage from an erased threshold voltage range to one of a plurality of programmed threshold voltage ranges
Grant 5,808,937 - Chi , et al. September 15, 1 | 1998-09-15 |
Bipolar-based active pixel sensor cell with metal contact and increased capacitive coupling to the base region
Grant 5,786,623 - Bergemont , et al. July 28, 1 | 1998-07-28 |
Single-poly EPROM cell that utilizes a reduced programming voltage to program the cell
Grant 5,761,126 - Chi , et al. June 2, 1 | 1998-06-02 |
Bipolar-based active pixel sensor cell with poly contact and increased capacitive coupling to the base region
Grant 5,760,458 - Bergemont , et al. June 2, 1 | 1998-06-02 |
Single-poly neuron MOS transistor
Grant 5,753,954 - Chi , et al. May 19, 1 | 1998-05-19 |
Active pixel sensor cell that utilizes a parasitic transistor to reset the photodiode of the cell
Grant 5,710,446 - Chi , et al. January 20, 1 | 1998-01-20 |
Method of erasing a high density contactless flash EPROM array
Grant 5,615,152 - Bergemont March 25, 1 | 1997-03-25 |
Single split-gate MOS transistor active pixel sensor cell with automatic anti-blooming and wide dynamic range
Grant 5,608,243 - Chi , et al. March 4, 1 | 1997-03-04 |
Method for programming a single EPROM or flash memory cell to store multiple bits of data that utilizes a punchthrough current
Grant 5,594,685 - Bergemont , et al. January 14, 1 | 1997-01-14 |
Single MOS transistor active pixel sensor cell with automatic anti-blooming and wide dynamic range
Grant 5,587,596 - Chi , et al. December 24, 1 | 1996-12-24 |
Method for programming an ETOX EPROM or flash memory when cells of the array are formed to store multiple bits of data
Grant 5,587,949 - Bergemont , et al. December 24, 1 | 1996-12-24 |
Base capacitor coupled photosensor with emitter tunnel oxide for very wide dynamic range in a contactless imaging array
Grant 5,566,044 - Bergemont , et al. October 15, 1 | 1996-10-15 |
Method for reducing the spacing between the horizontally-adjacent floating gates of a flash EPROM array
Grant 5,566,106 - Bergemont October 15, 1 | 1996-10-15 |
Method for programming an AMG EPROM or flash memory when cells of the array are formed to store multiple bits of data
Grant 5,557,567 - Bergemont , et al. September 17, 1 | 1996-09-17 |
Method for programming a single EPROM or flash memory cell to store multiple levels of data that utilizes a forward-biased source-to-substrate junction
Grant 5,511,021 - Bergemont , et al. April 23, 1 | 1996-04-23 |
Method of making increased-density flash EPROM that requires less area to form the metal bit line-to-drain contacts
Grant 5,484,741 - Bergemont January 16, 1 | 1996-01-16 |
Method for programming a single EPROM or FLASH memory cell to store multiple levels of data that utilizes a floating substrate
Grant 5,477,485 - Bergemont , et al. December 19, 1 | 1995-12-19 |
Memory array with field oxide islands eliminated and method
Grant 5,422,844 - Wolstenholme , et al. June 6, 1 | 1995-06-06 |
Increased-density flash EPROM that requires less area to form the metal bit line-to-drain contacts
Grant 5,416,349 - Bergemont May 16, 1 | 1995-05-16 |
Segment-erasable flash EPROM
Grant 5,397,726 - Bergemont * March 14, 1 | 1995-03-14 |
Method of controlling oxide thinning in an EPROM or flash memory array
Grant 5,397,725 - Wolstenholme , et al. March 14, 1 | 1995-03-14 |
High density EEPROM cell array with novel programming scheme and method of manufacture
Grant 5,379,253 - Bergemont * January 3, 1 | 1995-01-03 |
High density EEPROM cell with tunnel oxide stripe
Grant 5,293,331 - Hart , et al. March 8, 1 | 1994-03-08 |
Method of manufacturing a full feature high density EEPROM cell with poly tunnel spacer
Grant 5,225,362 - Bergemont July 6, 1 | 1993-07-06 |
Method of making large-scale EPROM memory with a checker board pattern and an improved coupling factor
Grant 5,047,362 - Bergemont September 10, 1 | 1991-09-10 |
Large-scale EPROM memory with a high coupling factor
Grant 5,012,446 - Bergemont April 30, 1 | 1991-04-30 |
Non-volatile memory with floating grid and without thick oxide
Grant 4,887,238 - Bergemont December 12, 1 | 1989-12-12 |
Method for contact between two conductive or semi-conductive layers deposited on a substrate
Grant 4,877,483 - Bergemont , et al. October 31, 1 | 1989-10-31 |
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