Ben-Meir; Amos

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ben-Meir; Amos.The latest application filed is for "multi-stage address translation for a computing device".

Company Profile

0.18.1

Ben-Meir; Amos - San Jose CA
Ben-Meir; Amos - Sunnyvale CA
Ben-Meir; Amos - Cupertino CA
Ben-Meir; Amos - Fremont CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Multi-stage address translation for a computing device Grant 10,210,096 - Ben-Meir Feb	2019-02-19
Method and apparatus for performing table lookup Grant 9,058,284 - Ben-Meir , et al. June 16, 2	2015-06-16
Multi-stage Address Translation For A Computing Device App 20150095610 - Ben-Meir; Amos	2015-04-02
Prefetch instruction mechanism for processor Grant 6,253,306 - Ben-Meir , et al. June 26, 2	2001-06-26
Unified multi-function operation scheduler for out-of-order execution in a superscaler processor Grant 6,195,744 - Favor , et al. February 27, 2	2001-02-27
Apparatus and method for a coincident rising edge detection circuit Grant 6,194,927 - Crowley , et al. February 27, 2	2001-02-27
Integration of multi-stage execution units with a scheduler for single-stage execution units Grant 6,161,173 - Krishna , et al. December 12, 2	2000-12-12
Scan chains for out-of-order load/store execution control Grant 6,038,657 - Favor , et al. March 14, 2	2000-03-14
Self-timed pulse control circuit Grant 5,964,884 - Partovi , et al. October 12, 1	1999-10-12
Register-based redundancy circuit and method for built-in self-repair in a semiconductor memory device Grant 5,920,515 - Shaik , et al. July 6, 1	1999-07-06
Unified multi-function operation scheduler for out-of-order execution in a superscalar processor Grant 5,884,059 - Favor , et al. March 16, 1	1999-03-16
Processing system that rapidly indentifies first or second operations of selected types for execution Grant 5,881,261 - Favor , et al. March 9, 1	1999-03-09
Self-modifying code handling system Grant 5,826,073 - Ben-Meir , et al. October 20, 1	1998-10-20
Instruction predecode and multiple instruction decode Grant 5,809,273 - Favor , et al. September 15, 1	1998-09-15
Out-of-order processing that removes an issued operation from an execution pipeline upon determining that the operation would cause a lengthy pipeline delay Grant 5,799,165 - Favor , et al. August 25, 1	1998-08-25
Out-of-order load/store execution control Grant 5,754,812 - Favor , et al. May 19, 1	1998-05-19
Partially decoded instruction cache Grant 5,669,011 - Alpert , et al. September 16, 1	1997-09-16
Apparatus and method for storing partially-decoded instructions in the instruction cache of a CPU having multiple execution units Grant 5,481,751 - Alpert , et al. January 2, 1	1996-01-02

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