loadpatents
name:-0.064923048019409
name:-0.059303998947144
name:-0.033060789108276
Belyansky; Michael P. Patent Filings

Belyansky; Michael P.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Belyansky; Michael P..The latest application filed is for "uniform horizontal spacer".

Company Profile
32.54.59
  • Belyansky; Michael P. - Halfmoon NY
  • Belyansky; Michael P - Bethel CT
  • Belyansky; Michael P. - Bethel CT
  • Belyansky; Michael P. - Clifton Park NY
  • Belyansky; Michael P. - Hopewell Junction NY US
  • Belyansky; Michael P. - Bethal CT
  • Belyansky; Michael P. - Danbury CT
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Threshold voltage adjustment from oxygen vacancy by scavenge metal filling at gate cut (CT)
Grant 11,282,962 - Zhou , et al. March 22, 2
2022-03-22
Self-aligned gate cap including an etch-stop layer
Grant 11,257,716 - Belyansky , et al. February 22, 2
2022-02-22
Self-aligned gate cap including an etch-stop layer
Grant 11,222,820 - Belyansky , et al. January 11, 2
2022-01-11
Vertical fin field effect transistor devices with a replacement metal gate
Grant 11,107,814 - Bao , et al. August 31, 2
2021-08-31
Vertical fin field effect transistor devices with a replacement metal gate
Grant 11,049,858 - Bao , et al. June 29, 2
2021-06-29
Vertical transport field-effect transistor (VFET) with dual top spacer
Grant 11,011,624 - Mochizuki , et al. May 18, 2
2021-05-18
Vertical fin field effect transistor devices with a replacement metal gate
Grant 11,004,850 - Bao , et al. May 11, 2
2021-05-11
Uniform Horizontal Spacer
App 20210119016 - Belyansky; Michael P. ;   et al.
2021-04-22
Uniform horizontal spacer
Grant 10,957,781 - Belyansky , et al. March 23, 2
2021-03-23
Transistor having straight bottom spacers
Grant 10,943,992 - Cheng , et al. March 9, 2
2021-03-09
Transistor Having Straight Bottom Spacers
App 20200357894 - Cheng; Kangguo ;   et al.
2020-11-12
Stress modulation of nFET and pFET fin structures
Grant 10,832,973 - Zhou , et al. November 10, 2
2020-11-10
Threshold Voltage Adjustment From Oxygen Vacancy By Scavenge Metal Filling At Gate Cut (ct)
App 20200287048 - Zhou; Huimei ;   et al.
2020-09-10
Stress Modulation Of Nfet And Pfet Fin Structures
App 20200266111 - Zhou; Huimei ;   et al.
2020-08-20
Controlling gate profile by inter-layer dielectric (ILD) nanolaminates
Grant 10,741,673 - Belyansky , et al. A
2020-08-11
Encapsulation layer for vertical transport field-effect transistor gate stack
Grant 10,741,663 - Bao , et al. A
2020-08-11
Highly selective dry etch process for vertical FET STI recess
Grant 10,734,245 - Bi , et al.
2020-08-04
Vertical Fin Field Effect Transistor Devices With A Replacement Metal Gate
App 20200243526 - Bao; Ruqiang ;   et al.
2020-07-30
Vertical Fin Field Effect Transistor Devices With A Replacement Metal Gate
App 20200243527 - Bao; Ruqiang ;   et al.
2020-07-30
Vertical Fin Field Effect Transistor Devices With A Replacement Metal Gate
App 20200243525 - Bao; Ruqiang ;   et al.
2020-07-30
Vertical fin field effect transistor devices with a replacement metal gate
Grant 10,679,993 - Bao , et al.
2020-06-09
Threshold voltage adjustment from oxygen vacancy by scavenge metal filling at gate cut (CT)
Grant 10,672,910 - Zhou , et al.
2020-06-02
Stress modulation of nFET and pFET fin structures
Grant 10,665,512 - Zhou , et al.
2020-05-26
Vertical Fin Field Effect Transistor Devices With A Replacement Metal Gate
App 20200144265 - Bao; Ruqiang ;   et al.
2020-05-07
Stress Modulation Of Nfet And Pfet Fin Structures
App 20200126867 - Zhou; Huimei ;   et al.
2020-04-23
Highly Selective Dry Etch Process for Vertical FET STI Recess
App 20200126805 - Bi; Zhenxing ;   et al.
2020-04-23
Self-aligned Gate Cap Including An Etch-stop Layer
App 20200090998 - Belyansky; Michael P. ;   et al.
2020-03-19
Protection of low temperature isolation fill
Grant 10,586,700 - Belyansky , et al.
2020-03-10
Threshold Voltage Adjustment From Oxygen Vacancy By Scavenge Metal Filling At Gate Cut (ct)
App 20200052125 - Zhou; Huimei ;   et al.
2020-02-13
Preventing Delamination At Silicon/dielectic Interface
App 20200051812 - Belyansky; Michael P. ;   et al.
2020-02-13
Uniform Horizontal Spacer
App 20200044054 - Belyansky; Michael P. ;   et al.
2020-02-06
Protection of low temperature isolation fill
Grant 10,535,550 - Belyansky , et al. Ja
2020-01-14
Self-aligned Gate Cap Including An Etch-stop Layer
App 20200006137 - Belyansky; Michael P. ;   et al.
2020-01-02
Vertical Transport FET (VFET) with Dual Top Spacer
App 20190334017 - Mochizuki; Shogo ;   et al.
2019-10-31
Vertical transport FET (VFET) with dual top spacer
Grant 10,388,766 - Mochizuki , et al. A
2019-08-20
Controlling Gate Profile By Inter-layer Dielectric (ild) Nanolaminates
App 20190207013 - Belyansky; Michael P. ;   et al.
2019-07-04
Vertical Transport FET (VFET) with Dual Top Spacer
App 20190123174 - Mochizuki; Shogo ;   et al.
2019-04-25
Controlling gate profile by inter-layer dielectric (ILD) nanolaminates
Grant 10,249,730 - Belyansky , et al.
2019-04-02
Protection Of Low Temperature Isolation Fill
App 20190067079 - Belyansky; Michael P. ;   et al.
2019-02-28
Protection Of Low Temperature Isolation Fill
App 20190067078 - Belyansky; Michael P. ;   et al.
2019-02-28
Uniform bottom spacer for vertical field effect transistor
Grant 10,170,582 - Belyansky , et al. J
2019-01-01
Resist having tuned interface hardmask layer for EUV exposure
Grant 10,141,188 - Belyansky , et al. Nov
2018-11-27
Resist having tuned interface hardmask layer for EUV exposure
Grant 10,134,592 - Belyansky , et al. November 20, 2
2018-11-20
Resist Having Tuned Interface Hardmask Layer For EUV Exposure
App 20180166277 - Belyansky; Michael P. ;   et al.
2018-06-14
Resist Having Tuned Interface Hardmask Layer For EUV Exposure
App 20180166278 - Belyansky; Michael P. ;   et al.
2018-06-14
Resist having tuned interface hardmask layer for EUV exposure
Grant 9,929,012 - Belyansky , et al. March 27, 2
2018-03-27
Self-aligned punchthrough stop doping in bulk finFET by reflowing doped oxide
Grant 9,613,956 - Belyansky , et al. April 4, 2
2017-04-04
Self-aligned punchthrough stop doping in bulk finFET by reflowing doped oxide
Grant 9,397,002 - Belyansky , et al. July 19, 2
2016-07-19
Dieletric Cap Having Material With Optical Band Gap To Substantially Block Uv Radiation During Curing Treatment, And Related Methods
App 20140302685 - Belyansky; Michael P. ;   et al.
2014-10-09
Methods Of Manufacturing Integrated Circuits Having A Compressive Nitride Layer
App 20140183720 - Beasor; Scott ;   et al.
2014-07-03
Method for controlling structure height
Grant 8,557,649 - Venigalla , et al. October 15, 2
2013-10-15
Method For Controlling Structure Height
App 20130102125 - Venigalla; Rajasekhar ;   et al.
2013-04-25
Method of patterned image reversal
Grant 8,420,542 - Sardesai , et al. April 16, 2
2013-04-16
Method Of Patterned Image Reversal
App 20120302069 - Sardesai; Viraj Yashawant ;   et al.
2012-11-29
Dual oxide stress liner
Grant 7,863,646 - Belyansky , et al. January 4, 2
2011-01-04
Structure and method to improve channel mobility by gate electrode stress modification
Grant 7,750,410 - Belyansky , et al. July 6, 2
2010-07-06
Oxidation method for altering a film structure
Grant 7,741,166 - Belyansky , et al. June 22, 2
2010-06-22
Method of forming gate stack and structure thereof
Grant 7,691,701 - Belyansky , et al. April 6, 2
2010-04-06
Field effect transistors (FETS) with inverted source/drain metallic contacts, and method of fabrication same
Grant 7,659,160 - Belyansky , et al. February 9, 2
2010-02-09
Field effect transistors (FETS) with inverted source/drain metallic contacts, and method of fabricating same
Grant 7,648,871 - Belyansky , et al. January 19, 2
2010-01-19
Field effect transistors with dielectric source drain halo regions and reduced miller capacitance
Grant 7,618,853 - Belyansky , et al. November 17, 2
2009-11-17
Method of producing highly strained PECVD silicon nitride thin films at low temperature
Grant 7,585,704 - Belyansky , et al. September 8, 2
2009-09-08
Mobility enhanced CMOS devices
Grant 7,569,848 - Belyansky , et al. August 4, 2
2009-08-04
Integration Of Ion Gettering Material In Dielectric
App 20090176350 - BELYANSKY; MICHAEL P. ;   et al.
2009-07-09
Ultraviolet Uv Photo Processing Or Curing Of Thin Films With Surface Treatment
App 20090155487 - BELYANSKY; MICHAEL P. ;   et al.
2009-06-18
Dual Oxide Stress Liner
App 20090152638 - BELYANSKY; MICHAEL P. ;   et al.
2009-06-18
Stressed semiconductor device structures having granular semiconductor material
Grant 7,488,658 - Doris , et al. February 10, 2
2009-02-10
Dielectric Cap Having Material With Optical Band Gap To Substantially Block Uv Radiation During Curing Treatment, And Related Methods
App 20080173985 - Belyansky; Michael P. ;   et al.
2008-07-24
Integrated Circuit System Having Strained Transistor
App 20080142897 - Teh; Young Way ;   et al.
2008-06-19
Stressed Semiconductor Device Structures Having Granular Semiconductor Material
App 20080064172 - Doris; Bruce B. ;   et al.
2008-03-13
Field effect transistors with dielectric source drain halo regions and reduced miller capacitance
Grant 7,342,266 - Belyansky , et al. March 11, 2
2008-03-11
Integrated Circuit System Having Strained Transistor
App 20080044967 - Teh; Young Way ;   et al.
2008-02-21
Field Effect Transistors (fets) With Inverted Source/drain Metallic Contacts, And Method Of Fabricating Same
App 20080042174 - Belyansky; Michael P. ;   et al.
2008-02-21
Field Effect Transistors With Dielectric Source Drain Halo Regions And Reduced Miller Capacitance
App 20080020522 - Belyansky; Michael P. ;   et al.
2008-01-24
Improved Thermal Budget Using Nickel Based Silicides For Enhanced Semiconductor Device Performance
App 20070249149 - Deshpande; Sadanand V. ;   et al.
2007-10-25
Method of forming self-aligned low-k gate cap
Grant 7,271,049 - Gluschenkov , et al. September 18, 2
2007-09-18
Field Effect Transistors With Dielectric Source Drain Halo Regions And Reduced Miller Capacitance
App 20070161169 - Belyansky; Michael P. ;   et al.
2007-07-12
Self-aligned low-k gate cap
Grant 7,230,296 - Gluschenkov , et al. June 12, 2
2007-06-12
Field Effect Transistors (fets) With Inverted Source/drain Metallic Contacts, And Method Of Fabricating Same
App 20070092990 - Belyansky; Michael P. ;   et al.
2007-04-26
Method of fabricating mobility enhanced CMOS devices
Grant 7,205,206 - Belyansky , et al. April 17, 2
2007-04-17
CMOS transistor structure including film having reduced stress by exposure to atomic oxygen
Grant 7,202,516 - Belyansky , et al. April 10, 2
2007-04-10
Multiple Low And High K Gate Oxides On Single Gate For Lower Miller Capacitance And Improved Drive Current
App 20070063277 - Belyansky; Michael P. ;   et al.
2007-03-22
Fabrication Of Strained Semiconductor-on-insulator (ssoi) Structures By Using Strained Insulating Layers
App 20070010070 - Belyansky; Michael P. ;   et al.
2007-01-11
Self-aligned low-k gate cap
App 20060289909 - Gluschenkov; Oleg ;   et al.
2006-12-28
Stressed semiconductor device structures having granular semiconductor material
Grant 7,122,849 - Doris , et al. October 17, 2
2006-10-17
Method Of Producing Highly Strained Pecvd Silicon Nitride Thin Films At Low Temperature
App 20060223290 - Belyansky; Michael P. ;   et al.
2006-10-05
Reduced dielectric constant spacer materials integration for high speed logic gates
Grant 7,081,393 - Belyansky , et al. July 25, 2
2006-07-25
Mobility enhanced CMOS devices
App 20060148147 - Belyansky; Michael P. ;   et al.
2006-07-06
CMOS transistor structure including film having reduced stress by exposure to atomic oxygen
App 20060131659 - Belyansky; Michael P. ;   et al.
2006-06-22
Oxidation method for altering a film structure
App 20060105516 - Belyansky; Michael P. ;   et al.
2006-05-18
SELF-ALIGNED LOW-k GATE CAP
App 20060099783 - Gluschenkov; Oleg ;   et al.
2006-05-11
Oxidation method for altering a film structure and CMOS transistor structure formed therewith
Grant 6,982,196 - Belyansky , et al. January 3, 2
2006-01-03
Structure and method to improve channel mobility by gate electrode stress modification
App 20050282325 - Belyansky, Michael P. ;   et al.
2005-12-22
Structure and method to improve channel mobility by gate electrode stress modification
Grant 6,977,194 - Belyansky , et al. December 20, 2
2005-12-20
Reduced Dielectric Constant Spacer Materials Integration For High Speed Logic Gates
App 20050260819 - Belyansky, Michael P. ;   et al.
2005-11-24
Forming collar structures in deep trench capacitors with thermally stable filler material
Grant 6,967,137 - Belyansky , et al. November 22, 2
2005-11-22
Structure and method to improve channel mobility by gate electrode stress modification
App 20050245017 - Belyansky, Michael P. ;   et al.
2005-11-03
Mobility Enhanced Cmos Devices
App 20050194699 - Belyansky, Michael P. ;   et al.
2005-09-08
Filling high aspect ratio isolation structures with polysilazane based material
App 20050179112 - Belyansky, Michael P. ;   et al.
2005-08-18
HDP process for high aspect ratio gap filling
Grant 6,914,015 - Belyansky , et al. July 5, 2
2005-07-05
Stressed Semiconductor Device Structures Having Granular Semiconductor Material
App 20050106799 - Doris, Bruce B. ;   et al.
2005-05-19
Oxidation Method For Altering A Film Structure And Cmos Transistor Structure Formed Therewith
App 20050093081 - Belyansky, Michael P. ;   et al.
2005-05-05
Structure and method to improve channel mobility by gate electrode stress modification
App 20050093059 - Belyansky, Michael P. ;   et al.
2005-05-05
Hdp Process For High Aspect Ratio Gap Filling
App 20050095872 - Belyansky, Michael P. ;   et al.
2005-05-05
Filling high aspect ratio isolation structures with polysilazane based material
Grant 6,869,860 - Belyansky , et al. March 22, 2
2005-03-22
Forming Collar Structures In Deep Trench Capacitors With Thermally Stable Filler Material
App 20050009267 - Belyansky, Michael P. ;   et al.
2005-01-13
Filling High Aspect Ratio Isolation Structures With Polysilazane Based Material
App 20040248374 - Belyansky, Michael P. ;   et al.
2004-12-09
Method of making thermally stable planarizing films
Grant 6,642,147 - Dokumaci , et al. November 4, 2
2003-11-04
Method of protecting semiconductor areas while exposing a gate
Grant 6,562,713 - Belyansky , et al. May 13, 2
2003-05-13
Method of making thermally stable planarizing films
App 20030038109 - Dokumaci, Omer H. ;   et al.
2003-02-27

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