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Patent applications and USPTO patent grants for Bellis; Andrew.The latest application filed is for "read-leveling implementations for ddr3 applications on an fpga".
Patent | Date |
---|---|
Integrated circuits with clock selection circuitry Grant 9,515,880 - Venkata , et al. December 6, 2 | 2016-12-06 |
Postamble timing for DDR memories Grant 7,990,783 - Clarke , et al. August 2, 2 | 2011-08-02 |
Read-leveling implementations for DDR3 applications on an FPGA Grant 7,990,786 - Chu , et al. August 2, 2 | 2011-08-02 |
PVT compensated auto-calibration scheme for DDR3 Grant 7,983,094 - Roge , et al. July 19, 2 | 2011-07-19 |
I/O block for high performance memory interfaces Grant 7,928,770 - Bellis , et al. April 19, 2 | 2011-04-19 |
Postamble timing for DDR memories Grant 7,876,630 - Clarke , et al. January 25, 2 | 2011-01-25 |
Read-leveling Implementations For Ddr3 Applications On An Fpga App 20090296503 - Chu; Michael H.M. ;   et al. | 2009-12-03 |
Read-leveling implementations for DDR3 applications on an FPGA Grant 7,593,273 - Chu , et al. September 22, 2 | 2009-09-22 |
PVT compensated auto-calibration scheme for DDR3 Grant 7,590,008 - Roge , et al. September 15, 2 | 2009-09-15 |
Dynamic control of memory interface timing Grant 7,589,556 - Tan , et al. September 15, 2 | 2009-09-15 |
Read-leveling Implementations For Ddr3 Applications On An Fpga App 20080291758 - Chu; Michael H.M. ;   et al. | 2008-11-27 |
Prefetching data based on predetermined criteria Grant 7,249,222 - Bellis , et al. July 24, 2 | 2007-07-24 |
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