Bellippady; Vidyadhara

Patent Applications and Registrations

Patent applications and USPTO patent grants for Bellippady; Vidyadhara.The latest application filed is for "non-volatile two-transistor programmable logic cell and array layout".

Company Profile

0.14.9

Bellippady; Vidyadhara - Cupertino CA
Bellippady; Vidyadhara - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Non-volatile two-transistor programmable logic cell and array layout Grant 8,258,567 - Dhaoui , et al. September 4, 2	2012-09-04
Array and control method for flash based FPGA cell Grant 8,120,955 - Wang , et al. February 21, 2	2012-02-21
Non-volatile Two-transistor Programmable Logic Cell And Array Layout App 20110147821 - Dhaoui; Fethi ; et al.	2011-06-23
Non-volatile two-transistor programmable logic cell and array layout Grant 7,956,404 - Dhaoui , et al. June 7, 2	2011-06-07
Non-volatile two-transistor programmable logic cell and array layout Grant 7,915,665 - Dhaoui , et al. March 29, 2	2011-03-29
Non-volatile two-transistor programmable logic cell and array layout Grant 7,898,018 - Dhaoui , et al. March 1, 2	2011-03-01
PLD providing soft wakeup logic Grant 7,884,640 - Greene , et al. February 8, 2	2011-02-08
Array And Control Method For Flash Based Fpga Cell App 20100208520 - Wang; Zhigang ; et al.	2010-08-19
Radiation-tolerant flash-based FPGA memory cells Grant 7,768,317 - Dhaoui , et al. August 3, 2	2010-08-03
Pld Providing Soft Wakeup Logic App 20100156457 - Greene; Jonathan W. ; et al.	2010-06-24
Non-volatile Two-transistor Programmable Logic Cell And Array Layout App 20100038697 - Dhaoui; Fethi ; et al.	2010-02-18
Non-volatile Two-transistor Programmable Logic Cell And Array Layout App 20090212343 - Dhaoui; Fethi ; et al.	2009-08-27
Non-volatile two-transistor programmable logic cell and array layout Grant 7,573,093 - Dhaoui , et al. August 11, 2	2009-08-11
Non-volatile Two-transistor Programmable Logic Cell And Array Layout App 20090159954 - Dhaoui; Fethi ; et al.	2009-06-25
Non-volatile two-transistor programmable logic cell and array layout Grant 7,538,382 - Dhaoui , et al. May 26, 2	2009-05-26
Non-volatile two-transistor programmable logic cell and array layout Grant 7,538,379 - Dhaoui , et al. May 26, 2	2009-05-26
Non-volatile memory with source-side column select Grant 7,522,453 - Wang , et al. April 21, 2	2009-04-21
Non-volatile two-transistor programmable logic cell and array layout Grant 7,501,681 - Dhaoui , et al. March 10, 2	2009-03-10
Non-volatile two-transistor programmable logic cell and array layout Grant 7,473,960 - Dhaoui , et al. January 6, 2	2009-01-06
Non-volatile Two-transistor Programmable Logic Cell And Array Layout App 20080093654 - Dhaoui; Fethi ; et al.	2008-04-24
Non-volatile two-transistor programmable logic cell and array layout Grant 7,285,818 - Dhaoui , et al. October 23, 2	2007-10-23
Non-volatile Two-transistor Programmable Logic Cell And Array Layout App 20070215935 - Dhaoui; Fethi ; et al.	2007-09-20
Non-volatile two-transistor programmable logic cell and array layout App 20060284238 - Dhaoui; Fethi ; et al.	2006-12-21

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