Bekele; Adebabay M.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Bekele; Adebabay M..The latest application filed is for "reconfigurable fractional-n frequency generation for a phase-locked loop".

Company Profile

4.20.7

Bekele; Adebabay M. - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Flexible wide-range and high bandwidth auxiliary clock and data recovery (CDR) circuit for transceivers Grant 10,868,663 - Turker Melek , et al. December 15, 2	2020-12-15
Multi-port inductors and transformers for accurately predicting voltage-controlled oscillator (VCO) frequency Grant 10,715,153 - Bekele , et al.	2020-07-14
Temperature-dependent phase-locked loop (PLL) reset for clock synthesizers Grant 10,630,301 - Bekele , et al.	2020-04-21
Reconfigurable fractional-N frequency generation for a phase-locked loop Grant 10,623,008 - Upadhyaya , et al.	2020-04-14
Phase-locked loop having sampling phase detector Grant 9,742,380 - Raj , et al. August 22, 2	2017-08-22
Phase-locked loop having sub-sampling phase detector Grant 9,608,644 - Raj , et al. March 28, 2	2017-03-28
Reconfigurable Fractional-n Frequency Generation For A Phase-locked Loop App 20160322979 - Upadhyaya; Parag ; et al.	2016-11-03
Voltage controlled oscillator including MuGFETS Grant 9,325,277 - Bekele , et al. April 26, 2	2016-04-26
Method and apparatus for powering down a dual supply current source Grant 8,614,599 - Bekele , et al. December 24, 2	2013-12-24
Method and apparatus for dividing clock frequencies Grant 8,218,712 - Jiang , et al. July 10, 2	2012-07-10
Integrated circuit having embedded differential clock tree Grant 7,759,973 - Vadi , et al. July 20, 2	2010-07-20
Differential clock tree in an integrated circuit Grant 7,518,401 - Vadi , et al. April 14, 2	2009-04-14
Programmable logic device having an embedded differential clock tree Grant 7,414,430 - Vadi , et al. August 19, 2	2008-08-19
Differential clock tree in an integrated circuit Grant 7,372,299 - Vadi , et al. May 13, 2	2008-05-13
High speed configurable transceiver architecture Grant 7,187,709 - Menon , et al. March 6, 2	2007-03-06
Differential clock tree in an integrated circuit App 20070013428 - Vadi; Vasisht Mantra ; et al.	2007-01-18
Differential clock tree in an integrated circuit App 20060290403 - Vadi; Vasisht Mantra ; et al.	2006-12-28
Programmable logic device having an embedded differential clock tree App 20060290402 - Vadi; Vasisht Mantra ; et al.	2006-12-28
Differential clocking scheme in an integrated circuit having digital multiplexers Grant 7,142,033 - Ghia , et al. November 28, 2	2006-11-28
Differential clock tree in an integrated circuit Grant 7,129,765 - Vadi , et al. October 31, 2	2006-10-31
Programmable logic device having an embedded differential clock tree Grant 7,126,406 - Vadi , et al. October 24, 2	2006-10-24
Differential clock driver circuit Grant 7,061,283 - Ghia , et al. June 13, 2	2006-06-13
Differential clock tree in an integrated circuit App 20050242865 - Vadi, Vasisht Mantra ; et al.	2005-11-03
Programmable logic device having an embedded differential clock tree App 20050242866 - Vadi, Vasisht Mantra ; et al.	2005-11-03
Differential clocking scheme in an integrated circuit having digital multiplexers App 20050242867 - Ghia, Atul V. ; et al.	2005-11-03
Low jitter clock for a physical media access sublayer on a field programmable gate array Grant 6,911,842 - Ghia , et al. June 28, 2	2005-06-28

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