Beilstein, Jr.; Kenneth E.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Beilstein, Jr.; Kenneth E..The latest application filed is for "structure for making sub-lithographic images by the intersection of two spacers".

Company Profile

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Beilstein, Jr.; Kenneth E. - Chittenden County VT
Beilstein, Jr.; Kenneth E. - Essex Junction VT
Beilstein, Jr.; Kenneth E. - Essex Center VT
Beilstein, Jr.; Kenneth E. - Essex VT
Beilstein, Jr.; Kenneth E. - Manassas VA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Structure for making sub-lithographic images by the intersection of two spacers Grant 5,920,101 - Beilstein, Jr. , et al. July 6, 1	1999-07-06
Structure for making sub-lithographic images by the intersection of two spacers Grant 5,834,818 - Beilstein, Jr. , et al. November 10, 1	1998-11-10
Method for making sub-lithographic images by etching the intersection of two spacers Grant 5,714,039 - Beilstein, Jr. , et al. February 3, 1	1998-02-03
Monolithic electronic modules--fabrication and structures Grant 5,614,277 - Beilstein, Jr. , et al. March 25, 1	1997-03-25
Semiconductor chip having a chip metal layer and a transfer metal and corresponding electronic module Grant 5,596,226 - Beilstein, Jr. , et al. January 21, 1	1997-01-21
Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging Grant 5,567,654 - Beilstein, Jr. , et al. October 22, 1	1996-10-22
Fabrication processes for monolithic electronic modules Grant 5,517,754 - Beilstein, Jr. , et al. May 21, 1	1996-05-21
Electronic modules with interconnected surface metallization layers Grant 5,517,057 - Beilstein, Jr. , et al. May 14, 1	1996-05-14
Electronic modules with interconnected surface metallization layers and fabrication methods therefore Grant 5,466,634 - Beilstein, Jr. , et al. November 14, 1	1995-11-14
Multichip integrated circuit packages and systems Grant 5,426,566 - Beilstein, Jr. , et al. June 20, 1	1995-06-20
Thermally enhanced semiconductor chip package Grant 5,309,318 - Beilstein, Jr. , et al. May 3, 1	1994-05-03
Process for positioning a mask within a concave semiconductor structure Grant 5,096,849 - Beilstein, Jr. , et al. March 17, 1	1992-03-17
DRAM memory cell having a horizontal SOI transfer device disposed over a buried storage node and fabrication methods therefor Grant 5,055,898 - Beilstein, Jr. , et al. October 8, 1	1991-10-08
Quaternary FET read only memory Grant RE32,401 - Beilstein, Jr. , et al. April 14, 1	1987-04-14
Method of making a MOSFET device with reduced sensitivity of threshold voltage to source to substrate voltage variations Grant 4,276,095 - Beilstein, Jr. , et al. June 30, 1	1981-06-30
Quaternary FET read only memory Grant 4,202,044 - Beilstein, Jr. , et al. May 6, 1	1980-05-06

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