BEATTIE; Bruce

Patent Applications and Registrations

Patent applications and USPTO patent grants for BEATTIE; Bruce.The latest application filed is for "cavity spacer for nanowire transistors".

Company Profile

4.7.9

BEATTIE; Bruce - Portland OR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Cavity Spacer For Nanowire Transistors App 20220246721 - HSU; William ; et al.	2022-08-04
Cavity spacer for nanowire transistors Grant 11,342,411 - Hsu , et al. May 24, 2	2022-05-24
Gate-all-around integrated circuit structures having self-aligned source or drain undercut for varied widths Grant 11,276,691 - Guha , et al. March 15, 2	2022-03-15
Self-aligned Nanowire App 20220052178 - Armstrong; Mark ; et al.	2022-02-17
Self-aligned nanowire Grant 11,205,715 - Armstrong , et al. December 21, 2	2021-12-21
Gate-all-around Integrated Circuit Structures Fabricated Using Alternate Etch Selective Material App 20210202479 - NASKAR; Sudipto ; et al.	2021-07-01
Self-aligned Nanowire App 20200152767 - Armstrong; Mark ; et al.	2020-05-14
Non-planar Integrated Circuit Structures Having Mitigated Source Or Drain Etch From Replacement Gate Process App 20200105757 - KANG; Jun Sung ; et al.	2020-04-02
Gate-all-around Integrated Circuit Structures Having Self-aligned Source Or Drain Undercut For Varied Widths App 20200091145 - GUHA; Biswajeet ; et al.	2020-03-19
Cavity Spacer For Nanowire Transistors App 20200006478 - Hsu; William ; et al.	2020-01-02
Nanowire Transistor Structure And Method Of Shaping App 20190393350 - Thompson; Erica J. ; et al.	2019-12-26
Methods of corrosion prevention and cleaning of copper structures App 20080152812 - Fang; Ming ; et al.	2008-06-26
Integrated circuit with multiple gate dielectric structures Grant 6,597,046 - Chau , et al. July 22, 2	2003-07-22
Post etch clean sequence for making a semiconductor device Grant 6,465,358 - Nashner , et al. October 15, 2	2002-10-15
Method of forming gate oxide having dual thickness by oxidation process Grant 6,124,171 - Arghavani , et al. September 26, 2	2000-09-26
Integrated circuit with multiple gate dielectric structures Grant 6,087,236 - Chau , et al. July 11, 2	2000-07-11

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