loadpatents
name:-0.038478136062622
name:-0.038367033004761
name:-0.026063919067383
Beasor; Scott Patent Filings

Beasor; Scott

Patent Applications and Registrations

Patent applications and USPTO patent grants for Beasor; Scott.The latest application filed is for "novel spacer structures for a transistor device".

Company Profile
24.29.27
  • Beasor; Scott - Greenwich NY
  • Beasor; Scott - Greenwick NY
  • Beasor; Scott - Rhinebeck NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
FinFET with etch-selective spacer and self-aligned contact capping layer
Grant 10,879,180 - Zang , et al. December 29, 2
2020-12-29
Spacer structures for a transistor device
Grant 10,872,979 - Zang , et al. December 22, 2
2020-12-22
Methods and structures for a gate cut
Grant 10,832,966 - Park , et al. November 10, 2
2020-11-10
Metal resistors with a non-planar configuration
Grant 10,832,839 - Beasor , et al. November 10, 2
2020-11-10
Fin reveal forming STI regions having convex shape between fins
Grant 10,832,965 - Xu , et al. November 10, 2
2020-11-10
FinFET having upper spacers adjacent gate and source/drain contacts
Grant 10,818,659 - Wang , et al. October 27, 2
2020-10-27
FinFET device and method of manufacturing
Grant 10,804,379 - Zang , et al. October 13, 2
2020-10-13
Transistor with a gate structure comprising a tapered upper surface
Grant 10,763,176 - Zang , et al. Sep
2020-09-01
Self-aligned sacrificial epitaxial capping for trench silicide
Grant 10,741,556 - Mulfinger , et al. A
2020-08-11
Asymmetric overlay mark for overlay measurement
Grant 10,707,175 - Zhao , et al.
2020-07-07
Novel Spacer Structures For A Transistor Device
App 20200168731 - Zang; Hui ;   et al.
2020-05-28
Chamfered replacement gate structures
Grant 10,636,890 - Wang , et al.
2020-04-28
Transistor With A Gate Structure Comprising A Tapered Upper Surface
App 20200126863 - Zang; Hui ;   et al.
2020-04-23
Methods of forming spacers adjacent gate structures of a transistor device
Grant 10,629,739 - Zang , et al.
2020-04-21
Gate contact and cross-coupling contact formation
Grant 10,629,694 - Zang , et al.
2020-04-21
Finfet Having Upper Spacers Adjacent Gate And Source/drain Contacts
App 20200119000 - Wang; Haiting ;   et al.
2020-04-16
Hybrid fin cut with improved fin profiles
Grant 10,586,736 - Wang , et al.
2020-03-10
Methods of making a self-aligned gate contact structure and source/drain metallization structures on integrated circuit products
Grant 10,580,701 - Zang , et al.
2020-03-03
Methods Of Forming Spacers Adjacent Gate Structures Of A Transistor Device
App 20200027979 - Zang; Hui ;   et al.
2020-01-23
Different upper and lower spacers for contact
Grant 10,522,644 - Xu , et al. Dec
2019-12-31
Different Upper And Lower Spacers For Contact
App 20190393321 - Xu; Guowei ;   et al.
2019-12-26
Hybrid Fin Cut With Improved Fin Profiles
App 20190378763 - WANG; Haiting ;   et al.
2019-12-12
Asymmetric Overlay Mark For Overlay Measurement
App 20190363053 - Zhao; Wei ;   et al.
2019-11-28
Finfet Device And Method Of Manufacturing
App 20190355838 - ZANG; Hui ;   et al.
2019-11-21
Chamfered Replacement Gate Structures
App 20190348517 - WANG; Haiting ;   et al.
2019-11-14
Scaled memory structures or other logic devices with middle of the line cuts
Grant 10,475,890 - Wang , et al. Nov
2019-11-12
Field-effect Transistors With Fins Formed By A Damascene-like Process
App 20190273148 - Zhao; Wei ;   et al.
2019-09-05
Field-effect transistors with fins formed by a damascene-like process
Grant 10,403,742 - Zhao , et al. Sep
2019-09-03
Methods And Structures For A Gate Cut
App 20190259668 - Park; Chang Seo ;   et al.
2019-08-22
Methods of forming source/drain contact structures on integrated circuit products
Grant 10,373,877 - Wang , et al.
2019-08-06
Gate oxide formation through hybrid methods of thermal and deposition processes and method for producing the same
Grant 10,361,289 - Zhao , et al.
2019-07-23
Single Work Function Enablement For Silicon Nanowire Device
App 20190221483 - MULFINGER; George ;   et al.
2019-07-18
Fin Reveal Forming Sti Regions Having Convex Shape Between Fins
App 20190214308 - Xu; Yiheng ;   et al.
2019-07-11
Self-aligned gate contact and cross-coupling contact formation
Grant 10,326,002 - Zang , et al.
2019-06-18
Finfet With Etch-selective Spacer And Self-aligned Contact Capping Layer
App 20190164898 - ZANG; Hui ;   et al.
2019-05-30
Scaled Memory Structures Or Other Logic Devices With Middle Of The Line Cuts
App 20190109197 - WANG; Haiting ;   et al.
2019-04-11
Field-effect Transistors With Fins Formed By A Damascene-like Process
App 20190097019 - Zhao; Wei ;   et al.
2019-03-28
Structure And Method For Capping Cobalt Contacts
App 20180277427 - SARDESAI; Viraj ;   et al.
2018-09-27
Self-aligned Sacrificial Epitaxial Capping For Trench Silicide
App 20180233505 - MULFINGER; George R. ;   et al.
2018-08-16
Method of manufacturing selective nanostructures into finFET process flow
Grant 10,049,944 - Beasor , et al. August 14, 2
2018-08-14
Structure and method for capping cobalt contacts
Grant 10,043,708 - Sardesai , et al. August 7, 2
2018-08-07
Silicon liner for STI CMP stop in FinFET
Grant 9,984,933 - Xu , et al. May 29, 2
2018-05-29
Structure And Method For Capping Cobalt Contacts
App 20180130703 - SARDESAI; Viraj ;   et al.
2018-05-10
Method Of Manufacturing Selective Nanostructures Into Finfet Process Flow
App 20180096899 - BEASOR; Scott ;   et al.
2018-04-05
Method Of Making Vertical And Bottom Bias E-fuses And Related Devices
App 20170338180 - BEASOR; Scott ;   et al.
2017-11-23
Self-aligned sacrificial epitaxial capping for trench silicide
Grant 9,812,453 - Mulfinger , et al. November 7, 2
2017-11-07
Metal-insulator-metal Capacitor Architecture
App 20160254345 - SINGH; Jagar ;   et al.
2016-09-01
Source/drain profile engineering for enhanced p-MOSFET
Grant 9,419,082 - Mishra , et al. August 16, 2
2016-08-16
Methods for fabricating FinFET integrated circuits with simultaneous formation of local contact openings
Grant 9,397,004 - Bouche , et al. July 19, 2
2016-07-19
Method for fabricating integrated circuits including contacts for metal resistors
Grant 9,330,971 - Beasor , et al. May 3, 2
2016-05-03
Source/drain Profile Engineering For Enhanced P-mosfet
App 20150311293 - MISHRA; Shiv Kumar ;   et al.
2015-10-29
Integrated Circuits Including Contacts For Metal Resistors And Methods For Fabricating The Same
App 20150255335 - Beasor; Scott ;   et al.
2015-09-10
Methods For Fabricating Finfet Integrated Circuits With Simultaneous Formation Of Local Contact Openings
App 20150214113 - Bouche; Guillaume ;   et al.
2015-07-30
Reusing active area mask for trench transfer exposure
Grant 8,962,485 - Salama , et al. February 24, 2
2015-02-24
Reusing Active Area Mask For Trench Transfer Exposure
App 20140342556 - Salama; Mohamed ;   et al.
2014-11-20
Methods Of Manufacturing Integrated Circuits Having A Compressive Nitride Layer
App 20140183720 - Beasor; Scott ;   et al.
2014-07-03

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