| Patent | Date |
|---|
Computing system with network attached processors
Grant 8,885,334 - Baxter November 11, 2 | 2014-11-11 |
Graphical user interface (GUI) including input files with information that determines representation of subsequent content displayed by the GUI
Grant 8,479,124 - Baxter , et al. July 2, 2 | 2013-07-02 |
Data storage system with removable memory module having parallel channels of DRAM memory and flash memory
Grant 8,134,875 - Baxter March 13, 2 | 2012-03-13 |
Port interface modules (PIMs) in a multi-port memory controller (MPMC)
Grant 7,913,022 - Baxter March 22, 2 | 2011-03-22 |
Accessing user registers in an integrated circuit
Grant 7,830,172 - Baxter November 9, 2 | 2010-11-09 |
Data Storage System With Removable Memory Module Having Parallel Channels Of Dram Memory And Flash Memory
App 20100142243 - Baxter; Glenn A. | 2010-06-10 |
Performance monitors (PMs) for measuring performance in a system and providing a record of transactions performed
Grant 7,720,636 - Baxter , et al. May 18, 2 | 2010-05-18 |
Self aligning state machine
Grant 7,711,907 - Baxter , et al. May 4, 2 | 2010-05-04 |
Data transfer using the configuration port of a programmable logic device
Grant 7,636,802 - Baxter December 22, 2 | 2009-12-22 |
Method and apparatus for communicating data between a network transceiver and memory circuitry
Grant 7,424,553 - Borrelli , et al. September 9, 2 | 2008-09-09 |
Programmable logic device including programmable interface core and central processing unit
Grant 7,406,557 - Dao , et al. July 29, 2 | 2008-07-29 |
Programmable logic device including programmable interface core and central processing unit
App 20070255886 - Dao; Khang Kim ; et al. | 2007-11-01 |
Programmable logic device including programmable interface core and central processing unit
Grant 7,266,632 - Dao , et al. September 4, 2 | 2007-09-04 |
Method and apparatus for controlling access to memory circuitry
Grant 7,260,688 - Baxter , et al. August 21, 2 | 2007-08-21 |
Method and apparatus for controlling direct access to memory circuitry
Grant 7,225,278 - Baxter , et al. May 29, 2 | 2007-05-29 |
Programmable logic device including programmable interface core and central processing unit
App 20060236018 - Dao; Khang Kim ; et al. | 2006-10-19 |
Programmable logic device including programmable interface core and central processing unit
Grant 7,076,595 - Dao , et al. July 11, 2 | 2006-07-11 |
Programmable logic device structures in standard cell devices
Grant 7,005,888 - Baxter February 28, 2 | 2006-02-28 |
Method and apparatus for timing management in a converted design
Grant 6,872,601 - Baxter , et al. March 29, 2 | 2005-03-29 |
Programmable logic device structures in standard cell devices
Grant 6,809,549 - Baxter October 26, 2 | 2004-10-26 |
Method and apparatus for timing management in a converted design
App 20040021490 - Baxter, Glenn A. ; et al. | 2004-02-05 |
Method for controlling timing in reduced programmable logic devices
Grant 6,675,309 - Baxter January 6, 2 | 2004-01-06 |
Method for managing database models for reduced programmable logic device components
Grant 6,629,308 - Baxter September 30, 2 | 2003-09-30 |
Method and apparatus for timing management in a converted design
Grant 6,625,787 - Baxter , et al. September 23, 2 | 2003-09-23 |
Programmable logic device structures in standard cell devices
App 20030080777 - Baxter, Glenn A. | 2003-05-01 |
Method for improving area in reduced programmable logic devices
Grant 6,526,563 - Baxter February 25, 2 | 2003-02-25 |
Programmable logic device structures in standard cell devices
Grant 6,515,509 - Baxter February 4, 2 | 2003-02-04 |
Method for converting programmable logic devices into standard cell devices
Grant 6,490,707 - Baxter December 3, 2 | 2002-12-03 |
Intelligent direct memory access controller providing controlwise and datawise intelligence for DMA transfers
Grant 6,370,601 - Baxter April 9, 2 | 2002-04-09 |
Programmable IC with gate array core and boundary scan capability
Grant 6,226,779 - Baxter , et al. May 1, 2 | 2001-05-01 |
Method for providing specific knowledge of a structure of parameter blocks to an intelligent direct memory access controller
Grant 6,202,106 - Baxter March 13, 2 | 2001-03-13 |
Hardwire logic device emulating an FPGA
Grant 6,120,551 - Law , et al. September 19, 2 | 2000-09-19 |
System and method for generating memory initialization logic in a target device with memory initialization bits from a programmable logic device
Grant 6,078,735 - Baxter June 20, 2 | 2000-06-20 |
Boundary scan chain with dedicated programmable routing
Grant 5,991,908 - Baxter , et al. November 23, 1 | 1999-11-23 |
Method and apparatus for converting a programmable logic device representation of a circuit into a second representation of the circuit
Grant 5,815,405 - Baxter September 29, 1 | 1998-09-29 |
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