Bautista, Jr.; Edward V.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Bautista, Jr.; Edward V..The latest application filed is for "implementation of recycling unused ecc parity bits during flash memory programming".

Company Profile

0.13.1

Bautista, Jr.; Edward V. - Sunnyvale CA
Bautista, Jr.; Edward V. - Santa Clara CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Implementation of recycling unused ECC parity bits during flash memory programming Grant 8,117,521 - Parker , et al. February 14, 2	2012-02-14
Implementation Of Recycling Unused Ecc Parity Bits During Flash Memory Programming App 20100058151 - Parker; Allan ; et al.	2010-03-04
Method and apparatus for pre-charging negative pump MOS regulation capacitors Grant 7,057,949 - Pan , et al. June 6, 2	2006-06-06
Diagnostic mode for testing functionality of BIST (built-in-self-test) back-end state machine Grant 7,028,240 - Bautista, Jr. , et al. April 11, 2	2006-04-11
Address sequencer within BIST (Built-in-Self-Test) system Grant 7,010,736 - Teh , et al. March 7, 2	2006-03-07
Memory device and method Grant 6,980,473 - Bautista, Jr. , et al. December 27, 2	2005-12-27
Memory device and method Grant 6,973,003 - Salleh , et al. December 6, 2	2005-12-06
CAM (content addressable memory) cells as part of core array in flash memory device Grant 6,970,368 - Bautista, Jr. , et al. November 29, 2	2005-11-29
Implementing reference current measurement mode within reference array programming mode or reference array erase mode in a semiconductor Grant 6,771,093 - Bautista, Jr. , et al. August 3, 2	2004-08-03
On-chip erase pulse counter for efficient erase verify BIST (built-in-self-test) mode Grant 6,665,214 - Cheah , et al. December 16, 2	2003-12-16
On-chip repair of defective address of core flash memory cells Grant 6,631,086 - Bill , et al. October 7, 2	2003-10-07
I/O partitioning system and methodology to reduce band-to-band tunneling current during erase Grant 6,385,093 - Bautista, Jr. , et al. May 7, 2	2002-05-07
Method and system for embedded chip erase verification Grant 6,331,951 - Bautista, Jr. , et al. December 18, 2	2001-12-18
Charge sharing to help boost the wordlines during APDE verify Grant 6,269,026 - Venkatesh , et al. July 31, 2	2001-07-31

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