BATUDE; Perrine

Patent Applications and Registrations

Patent applications and USPTO patent grants for BATUDE; Perrine.The latest application filed is for "three-dimensional microelectronic circuit with optimised distribution of its digital and analogue functions".

Company Profile

10.21.28

BATUDE; Perrine - Grenoble Cedex FR
Batude; Perrine - Grenoble FR
BATUDE; Perrine - Grenoble Cedex 09 FR
Batude; Perrine - Dijon FR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Three-dimensional Microelectronic Circuit With Optimised Distribution Of Its Digital And Analogue Functions App 20220093671 - SICARD; Gilles ; et al.	2022-03-24
Method Of Manufacturing An Optoelectronic Device Comprising A Plurality Of Diodes App 20210376185 - Batude; Perrine ; et al.	2021-12-02
3D circuit provided with mesa isolation for the ground plane zone Grant 11,139,209 - Batude , et al. October 5, 2	2021-10-05
Production of a 3D circuit with upper level transistor provided with a gate dielectric derived from a substrate transfer Grant 11,011,425 - Batude , et al. May 18, 2	2021-05-18
Image Sensor Formed In Sequential 3d Technology App 20210082983 - Kadura; Lina ; et al.	2021-03-18
3d Circuit Provided With Mesa Isolation For The Ground Plane Zone App 20200203229 - BATUDE; Perrine ; et al.	2020-06-25
Method Of Manufacturing An Optoelectronic Device Comprising A Plurality Of Diodes App 20200203422 - Batude; Perrine ; et al.	2020-06-25
3D circuit transistors with flipped gate Grant 10,651,202 - Andrieu , et al.	2020-05-12
Method for manufacturing pairs of CMOS transistors of the "fin-FET" type at low temperatures Grant 10,586,740 - Mathieu , et al.	2020-03-10
Transistor with controlled overlap of access regions Grant 10,553,702 - Batude , et al. Fe	2020-02-04
Production Of A 3d Circuit With Upper Level Transistor Provided With A Gate Dielectric Derived From A Substrate Transfer App 20200035561 - BATUDE; Perrine ; et al.	2020-01-30
Method of manufacturing a dopant transistor located vertically on the gate Grant 10,497,627 - Posseme , et al. De	2019-12-03
Integrated circuit having a plurality of active layers and method of fabricating the same Grant 10,319,628 - Deprat , et al.	2019-06-11
Method For Manufacturing Pairs Of Cmos Transistors Of The "fin-fet" Type At Low Temperatures App 20190157164 - MATHIEU; Benoit ; et al.	2019-05-23
3d Circuit Transistors With Flipped Gate App 20190157300 - ANDRIEU; Francois ; et al.	2019-05-23
3d Circuit With N And P Junctionless Transistors App 20190148367 - Colinge; Jean-Pierre ; et al.	2019-05-16
Method of making a transistor having a source and a drain obtained by recrystallization of semiconductor Grant 10,170,621 - Reboh , et al. J	2019-01-01
Method for doping source and drain regions of a transistor by means of selective amorphisation Grant 9,966,453 - Reboh , et al. May 8, 2	2018-05-08
Integrated Circuit Having A Plurality Of Active Layers And Method Of Fabricating The Same App 20180090366 - DEPRAT; Fabien ; et al.	2018-03-29
Method Of Making A Transistor Having A Source And A Drain Obtained By Recrystallization Of Semiconductor App 20170345931 - REBOH; Shay ; et al.	2017-11-30
Transistor With Controlled Overlap Of Access Regions App 20170301692 - BATUDE; Perrine ; et al.	2017-10-19
Fabrication method of a stack of electronic devices Grant 9,779,982 - Batude , et al. October 3, 2	2017-10-03
Method for producing strained semi-conductor blocks on the insulating layer of a semi-conductor on insulator substrate Grant 9,761,607 - Reboh , et al. September 12, 2	2017-09-12
Method Of Manufacturing A Dopant Transistor Located Vertically On The Gate App 20170221767 - POSSEME; Nicolas ; et al.	2017-08-03
Fabrication Method Of A Stack Of Electronic Devices App 20170178950 - BATUDE; Perrine ; et al.	2017-06-22
Method for producing a field effect transistor including forming a gate after forming the source and drain Grant 9,502,566 - Fenouillet-Beranger , et al. November 22, 2	2016-11-22
Method For Doping Source And Drain Regions Of A Transistor By Means Of Selective Amorphisation App 20160300927 - REBOH; Shay ; et al.	2016-10-13
Method for forming doped areas under transistor spacers Grant 9,379,213 - Batude , et al. June 28, 2	2016-06-28
Method For Making An Integrated Circuit In Three Dimensions App 20160181155 - DEPRAT; Fabien ; et al.	2016-06-23
Method for manufacturing a transistor in which the strain applied to the channel is increased Grant 9,343,375 - Batude , et al. May 17, 2	2016-05-17
Recrystallization of source and drain blocks from above Grant 9,246,006 - Batude , et al. January 26, 2	2016-01-26
Method To Fabricate A Transistor Wherein The Level Of Strain Applied To The Channel Is Enhanced App 20160020153 - BATUDE; Perrine ; et al.	2016-01-21
Method For Producing Strained Semi-conductor Blocks On The Insulating Layer Of A Semi-conductor On Insulator Substrate App 20150179665 - REBOH; Shay ; et al.	2015-06-25
Method of making a 3D integrated circuit Grant 9,018,078 - Sklenard , et al. April 28, 2	2015-04-28
Method For Producing A Transistor App 20150084095 - FENOUILLET-BERANGER; Claire ; et al.	2015-03-26
Recrystallization Of Source And Drain Blocks From Above App 20150044828 - BATUDE; Perrine ; et al.	2015-02-12
Method For Forming Doped Areas Under Transistor Spacers App 20150044841 - BATUDE; Perrine ; et al.	2015-02-12
Integrated circuit with electrostatically coupled MOS transistors and method for producing such an integrated circuit Grant 8,853,785 - Augendre , et al. October 7, 2	2014-10-07
Method for forming a via contacting several levels of semiconductor layers Grant 8,722,471 - Batude , et al. May 13, 2	2014-05-13
Integrated Circuit Having A Junctionless Depletion-mode Fet Device App 20130203248 - Ernst; Thomas ; et al.	2013-08-08
Method For Forming A Via Contacting Several Levels Of Semiconductor Layers App 20130196500 - Batude; Perrine ; et al.	2013-08-01
3d Integrated Circuit App 20130193550 - Sklenard; Benoit ; et al.	2013-08-01
Circuit with transistors integrated in three dimensions and having a dynamically adjustable threshold voltage VT Grant 8,183,630 - Batude , et al. May 22, 2	2012-05-22
SRAM memory cell having transistors integrated at several levels and the threshold voltage VT of which is dynamically adjustable Grant 8,013,399 - Thomas , et al. September 6, 2	2011-09-06
Integrated Circuit With Electrostatically Coupled Mos Transistors And Method For Producing Such An Integrated Circuit App 20110147849 - AUGENDRE; Emmanuel ; et al.	2011-06-23
Sram Memory Cell Having Transistors Integrated At Several Levels And The Threshold Voltage Vt Of Which Is Dynamically Adjustable App 20090294861 - THOMAS; Olivier ; et al.	2009-12-03
Circuit With Transistors Integrated In Three Dimensions And Having A Dynamically Adjustable Threshold Voltage Vt App 20090294822 - Batude; Perrine ; et al.	2009-12-03

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