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Patent applications and USPTO patent grants for Batra; Pooja R..The latest application filed is for "combination of tsv and back side wiring in 3d integration".
Patent | Date |
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Double-sided segmented line architecture in 3D integration Grant 9,870,979 - Batra , et al. January 16, 2 | 2018-01-16 |
Double-sided segmented line architecture in 3D integration Grant 9,559,040 - Batra , et al. January 31, 2 | 2017-01-31 |
Combination of TSV and back side wiring in 3D integration Grant 9,543,229 - Batra , et al. January 10, 2 | 2017-01-10 |
Combination of TSV and back side wiring in 3D integration Grant 9,536,809 - Batra , et al. January 3, 2 | 2017-01-03 |
Semiconductor structure having buried conductive elements Grant 9,263,454 - Alptekin , et al. February 16, 2 | 2016-02-16 |
Semiconductor structure having buried conductive elements Grant 9,245,892 - Alptekin , et al. January 26, 2 | 2016-01-26 |
Combination Of Tsv And Back Side Wiring In 3d Integration App 20150371927 - Batra; Pooja R. ;   et al. | 2015-12-24 |
Double-sided Segmented Line Architecture In 3d Integration App 20150364401 - Batra; Pooja R. ;   et al. | 2015-12-17 |
Semiconductor Structure Having Buried Conductive Elements App 20150364476 - Alptekin; Emre ;   et al. | 2015-12-17 |
Semiconductor Structure Having Buried Conductive Elements App 20150236024 - Alptekin; Emre ;   et al. | 2015-08-20 |
Double-sided Segmented Line Architecture In 3d Integration App 20150187642 - Batra; Pooja R. ;   et al. | 2015-07-02 |
Combination Of Tsv And Back Side Wiring In 3d Integration App 20150187733 - Batra; Pooja R. ;   et al. | 2015-07-02 |
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