loadpatents
name:-0.025985956192017
name:-0.025945901870728
name:-0.0074708461761475
Bartling; Steven C. Patent Filings

Bartling; Steven C.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Bartling; Steven C..The latest application filed is for "piezo-electric sensor reset".

Company Profile
6.24.28
  • Bartling; Steven C. - Dallas TX
  • Bartling; Steven C. - Plano TX
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Differential sensor using thin-film piezoelectric capacitors
Grant 11,393,971 - Khanna , et al. July 19, 2
2022-07-19
Piezo-electric Sensor Reset
App 20210389174 - Zwerg; Michael ;   et al.
2021-12-16
Piezo-electric sensor reset
Grant 11,105,676 - Zwerg , et al. August 31, 2
2021-08-31
Piezoelectric sensing apparatus and method
Grant 10,873,020 - Shih , et al. December 22, 2
2020-12-22
Enhanced immunity latched logic state retention
Grant 10,734,978 - Purushothaman , et al.
2020-08-04
Enhanced Immunity Latched Logic State Retention
App 20200212896 - Purushothaman; Soman ;   et al.
2020-07-02
Differential Sensor Using Thin-film Piezoelectric Capacitors
App 20200168786 - Khanna; Sudhanshu ;   et al.
2020-05-28
Piezo-electric Sensor Reset
App 20190162590 - Zwerg; Michael ;   et al.
2019-05-30
Piezoelectric Sensing Apparatus and Method
App 20190051812 - Shih; Wei-Yan ;   et al.
2019-02-14
Dual-port negative level sensitive preset data retention latch
Grant 9,520,863 - Bartling , et al. December 13, 2
2016-12-13
Dual-port negative level sensitive reset preset data retention latch
Grant 9,520,862 - Bartling , et al. December 13, 2
2016-12-13
Dual-port positive level sensitive reset preset data retention latch
Grant 9,018,976 - Bartling , et al. April 28, 2
2015-04-28
Dual-port positive level sensitive preset data retention latch
Grant 9,007,091 - Bartling , et al. April 14, 2
2015-04-14
Dual-port Negative Level Sensitive Reset Preset Data Retention Latch
App 20150070061 - Bartling; Steven C. ;   et al.
2015-03-12
Dual-port Positive Level Sensitive Preset Data Retention Latch
App 20150054544 - Bartling; Steven C. ;   et al.
2015-02-26
Dual-port Positive Level Sensitive Reset Preset Data Retention Latch
App 20150054545 - Bartling; Steven C. ;   et al.
2015-02-26
Dual-port Negative Level Sensitive Preset Data Retention Latch
App 20150054557 - Bartling; Steven C. ;   et al.
2015-02-26
Digital storage element architecture comprising integrated 2-to-1 multiplexer functionality
Grant 8,692,592 - Branch , et al. April 8, 2
2014-04-08
Scan testable register file
Grant 7,908,535 - Branch , et al. March 15, 2
2011-03-15
Scan Testable Register File
App 20100332929 - Branch; Charles M. ;   et al.
2010-12-30
Digital design component with scan clock generation
Grant 7,650,549 - Branch , et al. January 19, 2
2010-01-19
Method and system for correcting signal integrity crosstalk violations
Grant 7,644,383 - Bartling , et al. January 5, 2
2010-01-05
Systems and devices for implementing sub-threshold memory devices
Grant 7,626,850 - Branch , et al. December 1, 2
2009-12-01
Digital storage element architecture comprising dual scan clocks and gated scan output
Grant 7,596,732 - Branch , et al. September 29, 2
2009-09-29
Pipelined access by FFT and filter units in co-processor and system bus slave to memory blocks via switch coupling based on control register content
Grant 7,587,577 - Royer , et al. September 8, 2
2009-09-08
Digital storage element with enable signal gating
Grant 7,487,417 - Branch , et al. February 3, 2
2009-02-03
Wirelessly Transmitting Biological Parameters
App 20090015413 - GELABERT; Pedro R. ;   et al.
2009-01-15
Systems and Devices for Implementing Sub-Threshold Memory Devices
App 20080259681 - Branch; Charles M. ;   et al.
2008-10-23
Systems and Devices for Sub-threshold Data Capture
App 20080258790 - Branch; Charles M. ;   et al.
2008-10-23
Apparatus and method for generating pulses
Grant 7,425,859 - Branch , et al. September 16, 2
2008-09-16
Digital storage element architecture comprising dual scan clocks and preset functionality
Grant 7,375,567 - Branch , et al. May 20, 2
2008-05-20
Digital storage element with dual behavior
Grant 7,345,518 - Branch , et al. March 18, 2
2008-03-18
Digital storage element architecture comprising dual scan clocks and reset functionality
Grant 7,315,191 - Branch , et al. January 1, 2
2008-01-01
Apparatus And Method For Generating Pulses
App 20070229135 - Branch; Charles M. ;   et al.
2007-10-04
Digital storage element architecture comprising integrated 4-to-1 multiplexer functionality
Grant 7,274,233 - Branch , et al. September 25, 2
2007-09-25
Digital storage element architecture comprising integrated multiplexer and reset functionality
Grant 7,274,234 - Branch , et al. September 25, 2
2007-09-25
Apparatus and method for generating pulses
Grant 7,236,036 - Branch , et al. June 26, 2
2007-06-26
Low-Power Co-Processor Architecture
App 20070113048 - Royer; Marc E. ;   et al.
2007-05-17
Digital design component with scan clock generation
App 20070022339 - Branch; Charles M. ;   et al.
2007-01-25
Digital storage element architecture comprising dual scan clocks and gated scan output
App 20070022344 - Branch; Charles M. ;   et al.
2007-01-25
Digital storage element with enable signal gating
App 20070022336 - Branch; Charles M. ;   et al.
2007-01-25
Digital storage element with dual behavior
App 20070001732 - Branch; Charles M. ;   et al.
2007-01-04
Digital storage element architecture comprising dual scan clocks and preset functionality
App 20070001729 - Branch; Charles M. ;   et al.
2007-01-04
Digital storage element architecture comprising integrated 4-to-1 multiplexer functionality
App 20070001730 - Branch; Charles M. ;   et al.
2007-01-04
Digital storage element architecture comprising integrated multiplexer and reset functionality
App 20070001731 - Branch; Charles M. ;   et al.
2007-01-04
Method and system for synthesis of flip-flops
App 20070006105 - Bartling; Steven C. ;   et al.
2007-01-04
Method and system for desensitization of chip designs from perturbations affecting timing and manufacturability
App 20070006106 - Bartling; Steven C. ;   et al.
2007-01-04
Digital storage element architecture comprising dual scan clocks and reset functionality
App 20070001728 - Branch; Charles M. ;   et al.
2007-01-04
Method and system for correcting signal integrity crosstalk violations
App 20070006109 - Bartling; Steven C. ;   et al.
2007-01-04
Digital storage element architecture comprising integrated 2-to-1 multiplexer functionality
App 20070001733 - Branch; Charles M. ;   et al.
2007-01-04
Apparatus and method for generating pulses
App 20060226885 - Branch; Charles M. ;   et al.
2006-10-12
Company Registrations
SEC0001390622BARTLING STEVEN C

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed