Bartenstein; Thomas W.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Bartenstein; Thomas W..The latest application filed is for "isolating the location of defects in scan chains".
- Bartenstein; Thomas W. - Owego NY US
| Patent | Date |
|---|---|
| Method and system for identifying power defects using test pattern switching activity Grant 8,397,113 - Bartenstein , et al. March 12, 2 | 2013-03-12 |
| Isolating the location of defects in scan chains Grant 7,496,816 - Bartenstein , et al. February 24, 2 | 2009-02-24 |
| Isolating the location of defects in scan chains App 20070220384 - Bartenstein; Thomas W. ; et al. | 2007-09-20 |
| Internal cache for on chip test data storage Grant 6,901,542 - Bartenstein , et al. May 31, 2 | 2005-05-31 |
| Diagnosis of combinational logic circuit failures Grant 6,721,914 - Bartenstein , et al. April 13, 2 | 2004-04-13 |
| Method for diagnosing failures using invariant analysis Grant 6,708,306 - Bartenstein , et al. March 16, 2 | 2004-03-16 |
| Incremental fault dictionary Grant 6,675,323 - Bartenstein , et al. January 6, 2 | 2004-01-06 |
| Incremental fault dictionary App 20030046608 - Bartenstein, Thomas W. ; et al. | 2003-03-06 |
| Internal cache for on chip test data storage App 20030033566 - Bartenstein, Thomas W. ; et al. | 2003-02-13 |
| Efficiency of fault simulation by logic backtracking App 20020188904 - Chen, Xinghao ; et al. | 2002-12-12 |
| Diagnosis of combinational logic circuit failures App 20020147952 - Bartenstein, Thomas W. ; et al. | 2002-10-10 |
| Method for diagnosing failures using invariant analysis App 20020120891 - Bartenstein, Thomas W. ; et al. | 2002-08-29 |
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