Barsan; Radu

Patent Applications and Registrations

Patent applications and USPTO patent grants for Barsan; Radu.The latest application filed is for "device fabrication with planar bragg gratings suppressing parasitic effects".

Company Profile

0.11.2

Barsan; Radu - Saratoga CA US
Barsan; Radu - Cupertino CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Device fabrication with planar bragg gratings suppressing parasitic effects Grant 8,358,889 - Barsan , et al. January 22, 2	2013-01-22
Device Fabrication With Planar Bragg Gratings Suppressing Parasitic Effects App 20100303411 - Barsan; Radu ; et al.	2010-12-02
Improving Field Leakage By Using A Thin Layer Of Nitride Deposited By Chemical Vapor Deposition App 20020000626 - LIN, JONATHAN ; et al.	2002-01-03
Annealing of silicon oxynitride and silicon nitride films to eliminate high temperature charge loss Grant 6,071,784 - Mehta , et al. June 6, 2	2000-06-06
Data retention of EEPROM cell with shallow trench isolation using thicker liner oxide Grant 6,064,105 - Li , et al. May 16, 2	2000-05-16
Data retention of EEPROM cell with shallow trench isolation using thicker liner oxide Grant 5,854,114 - Li , et al. December 29, 1	1998-12-29
Simplified masking process for programmable logic device manufacture Grant 5,830,795 - Mehta , et al. November 3, 1	1998-11-03
Method for screening non-volatile memory and programmable logic devices Grant 5,700,698 - Barsan , et al. December 23, 1	1997-12-23
CMOS memory cell with tunneling during program and erase through the NMOS and PMOS transistors and a pass gate separating the NMOS and PMOS transistors Grant 5,646,901 - Sharpe-Geisler , et al. July 8, 1	1997-07-08
Control gate-addressed CMOS non-volatile cell that programs through gates of CMOS transistors Grant 5,615,150 - Lin , et al. March 25, 1	1997-03-25
Completely complementary MOS memory cell with tunneling through the NMOS and PMOS transistors during program and erase Grant 5,594,687 - Lin , et al. January 14, 1	1997-01-14
CMOS EEPROM cell with tunneling window in the read path Grant 5,587,945 - Lin , et al. December 24, 1	1996-12-24

Company Registrations

SEC

0001583052

Barsan Radu

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.