Barroso; Luiz A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Barroso; Luiz A..The latest application filed is for "multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants".

Company Profile

0.9.9

Barroso; Luiz A. - Mountain View CA

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Patent Activity

Patent	Date
System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system Grant 7,389,389 - Gharachorloo , et al. June 17, 2	2008-06-17
Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants Grant 6,925,537 - Barroso , et al. August 2, 2	2005-08-02
Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants App 20040148472 - Barroso, Luiz A. ; et al.	2004-07-29
Scalable multiprocessor system and cache coherence method Grant 6,751,710 - Gharachorloo , et al. June 15, 2	2004-06-15
System and method for generating cache coherence directory entries and error correction codes in a multiprocessor system Grant 6,725,343 - Barroso , et al. April 20, 2	2004-04-20
System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system App 20040064653 - Gharachorloo, Kourosh ; et al.	2004-04-01
System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system Grant 6,697,919 - Gharachorloo , et al. February 24, 2	2004-02-24
Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants Grant 6,675,265 - Barroso , et al. January 6, 2	2004-01-06
System for handling coherence protocol races in a scalable shared memory system based on chip multiprocessing Grant 6,636,949 - Barroso , et al. October 21, 2	2003-10-21
Cache coherence protocol engine system and method for processing memory transaction in distinct address subsets during interleaved time periods in a multiprocessor system Grant 6,622,217 - Gharachorloo , et al. September 16, 2	2003-09-16
Cache coherence protocol engine and method for efficient processing of interleaved memory transactions in a multiprocessor system Grant 6,622,218 - Gharachorloo , et al. September 16, 2	2003-09-16
System for handling coherence protocol races in a scalable shared memory system based on chip multiprocessing App 20020129208 - Barroso, Luiz A. ; et al.	2002-09-12
System and method for generating cache coherence directory entries and error correction codes in a multiprocessor system App 20020124143 - Barroso, Luiz A. ; et al.	2002-09-05
Cache coherence protocol engine and method for efficient processing of interleaved memory transactions in a multiprocessor system App 20020087806 - Gharachorloo, Kourosh ; et al.	2002-07-04
Cache coherence protocol engine and method for processing memory transaction in distinct address subsets during interleaved time periods in a multiprocessor system App 20020046327 - Gharachorloo, Kourosh ; et al.	2002-04-18
Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants App 20020010840 - Barroso, Luiz A. ; et al.	2002-01-24
System and method for limited fanout daisy chaining of cache invalidation requests in a shared-memory multiprocessor system App 20020007439 - Gharachorloo, Kourosh ; et al.	2002-01-17
Scalable multiprocessor system and cache coherence method App 20020007443 - Gharachorloo, Kourosh ; et al.	2002-01-17

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