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Patent applications and USPTO patent grants for Barrett; Geoff.The latest application filed is for "asynchronous clock domain crossing jitter randomiser".
Patent | Date |
---|---|
Interrupt verification support mechanism Grant 7,765,388 - Barrett , et al. July 27, 2 | 2010-07-27 |
Asynchronous clock domain crossing jitter randomiser Grant 7,640,151 - Smith , et al. December 29, 2 | 2009-12-29 |
Method and system for realizing a logic model design Grant 7,567,892 - Barrett , et al. July 28, 2 | 2009-07-28 |
Method and apparatus for restructuring a binary decision diagram Grant 7,149,663 - Barrett December 12, 2 | 2006-12-12 |
Method of generating a test suite Grant 7,143,073 - Barrett November 28, 2 | 2006-11-28 |
Asynchronous clock domain crossing jitter randomiser App 20050222832 - Smith, Simon ;   et al. | 2005-10-06 |
Interrupt verification support mechanism App 20050060577 - Barrett, Geoff ;   et al. | 2005-03-17 |
Post image techniques Grant 6,816,821 - Barrett November 9, 2 | 2004-11-09 |
Method and system for realizing a logic model design App 20030225557 - Barrett, Geoff ;   et al. | 2003-12-04 |
Method of generating a test suite App 20030191985 - Barrett, Geoff | 2003-10-09 |
Post image techniques Grant 6,031,983 - Barrett February 29, 2 | 2000-02-29 |
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