Barr; Alexander L.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Barr; Alexander L..The latest application filed is for "method for forming a semiconductor structure having a strained silicon layer".

Company Profile

0.20.20

Barr; Alexander L. - Crolles FR
Barr; Alexander L. - Austin TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method for making a semiconductor structure using silicon germanium Grant 7,927,956 - Orlowski , et al. April 19, 2	2011-04-19
Method for forming a semiconductor structure having a strained silicon layer Grant 7,811,382 - Sadaka , et al. October 12, 2	2010-10-12
Semiconductor device structure Grant 7,781,840 - White , et al. August 24, 2	2010-08-24
Method For Forming A Semiconductor Structure Having A Strained Silicon Layer App 20070277728 - Sadaka; Mariam G. ; et al.	2007-12-06
Method of making a dual strained channel semiconductor device Grant 7,282,402 - Sadaka , et al. October 16, 2	2007-10-16
Semiconductor Device Structure And Method Therefor App 20070235807 - White; Ted R. ; et al.	2007-10-11
Graded semiconductor layer Grant 7,241,647 - Sadaka , et al. July 10, 2	2007-07-10
Semiconductor device structure and method therefor Grant 7,226,833 - White , et al. June 5, 2	2007-06-05
Template layer formation Grant 7,208,357 - Sadaka , et al. April 24, 2	2007-04-24
Semiconductor structure having strained semiconductor and method therefor Grant 7,205,210 - Barr , et al. April 17, 2	2007-04-17
Method For Making A Semiconductor Structure Using Silicon Germanium App 20070082453 - Orlowski; Marius K. ; et al.	2007-04-12
Method for making a semiconductor structure using silicon germanium Grant 7,163,903 - Orlowski , et al. January 16, 2	2007-01-16
Channel orientation to enhance transistor performance Grant 7,160,769 - White , et al. January 9, 2	2007-01-09
Method of making a dual strained channel semiconductor device App 20060228851 - Sadaka; Mariam G. ; et al.	2006-10-12
Double gate device having a heterojunction source/drain and strained channel Grant 7,067,868 - Thean , et al. June 27, 2	2006-06-27
Semiconductor layer formation Grant 7,056,778 - Liu , et al. June 6, 2	2006-06-06
Method for forming a semiconductor device with local semiconductor-on-insulator (SOI) Grant 7,045,432 - Orlowski , et al. May 16, 2	2006-05-16
Semiconductor device structure and method therefor App 20060094169 - White; Ted R. ; et al.	2006-05-04
Low RC product transistors in SOI semiconductor process Grant 7,037,795 - Barr , et al. May 2, 2	2006-05-02
Channel orientation to enhance transistor performance App 20060084207 - White; Ted R. ; et al.	2006-04-20
Low Rc Product Transistors In Soi Semiconductor Process App 20060084235 - Barr; Alexander L. ; et al.	2006-04-20
Method of manufacturing SOI template layer Grant 7,029,980 - Liu , et al. April 18, 2	2006-04-18
Double gate device having a heterojunction source/drain and strained channel App 20060065927 - Thean; Voon-Yew ; et al.	2006-03-30
Method For Forming A Semiconductor Device Having A Strained Channel And A Heterojunction Source/drain App 20060068553 - Thean; Voon-Yew ; et al.	2006-03-30
Method for forming a semiconductor device having a strained channel and a heterojunction source/drain Grant 7,018,901 - Thean , et al. March 28, 2	2006-03-28
Graded semiconductor layer App 20060040433 - Sadaka; Mariam G. ; et al.	2006-02-23
Method for forming a semiconductor device having isolation regions Grant 6,964,911 - Orlowski , et al. November 15, 2	2005-11-15
Method for making a semiconductor structure using silicon germanium App 20050245092 - Orlowski, Marius K. ; et al.	2005-11-03
Semiconductor structure having strained semiconductor and method therefor App 20050181549 - Barr, Alexander L. ; et al.	2005-08-18
Method for forming a semiconductor device with local semiconductor-on-insulator (SOI) App 20050170604 - Orlowski, Marius K. ; et al.	2005-08-04
SOI template layer App 20050070056 - Liu, Chun-Li ; et al.	2005-03-31
Semiconductor layer formation App 20050070057 - Liu, Chun-Li ; et al.	2005-03-31
Template layer formation App 20050070053 - Sadaka, Mariam G. ; et al.	2005-03-31
Method for forming a semiconductor device having isolation regions App 20050064669 - Orlowski, Marius K. ; et al.	2005-03-24
Method for forming a double-gated semiconductor device Grant 6,838,322 - Pham , et al. January 4, 2	2005-01-04
Semiconductor structure with different lattice constant materials and method for forming the same Grant 6,831,350 - Liu , et al. December 14, 2	2004-12-14
Method For Forming A Double-gated Semiconductor Device App 20040219722 - Pham, Daniel T. ; et al.	2004-11-04
Method of forming semiconductor device including interconnect barrier layers Grant 6,713,381 - Barr , et al. March 30, 2	2004-03-30
Semiconductor device and method of formation App 20020093098 - Barr, Alexander L. ; et al.	2002-07-18
Semiconductor Device Conductive Bump And Interconnect Barrier App 20020000665 - BARR, ALEXANDER L. ; et al.	2002-01-03

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