Barowski; Harry

Patent Applications and Registrations

Patent applications and USPTO patent grants for Barowski; Harry.The latest application filed is for "erasing a partition of an sram array with hardware support".

Company Profile

25.58.53

Barowski; Harry - Schoenaich DE
Barowski; Harry - Boeblingen DE
Barowski; Harry - Beoblingen DE
Barowski; Harry - Boblingen N/A DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Erasing A Partition Of An Sram Array With Hardware Support App 20220013166 - Schmidt; Martin Bernhard ; et al.	2022-01-13
Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature Grant 11,043,938 - Barowski , et al. June 22, 2	2021-06-22
RAM memory with pre-charging circuitry coupled to global bit-lines and method for reducing power consumption Grant 10,984,843 - Schmidt , et al. April 20, 2	2021-04-20
Integrated circuit design changes using through-silicon vias Grant 10,956,644 - Barowski , et al. March 23, 2	2021-03-23
Global bit line latch performance and power optimization Grant 10,832,763 - Schmidt , et al. November 10, 2	2020-11-10
Reducing Memory Power Consumption App 20200279593 - Schmidt; Martin Bernhard ; et al.	2020-09-03
Global Bit Line Latch Performance And Power Optimization App 20200194060 - Schmidt; Martin Bernhard ; et al.	2020-06-18
Qubit Tuning By Magnetic Fields In Superconductors App 20200167684 - Frisch; Albert ; et al.	2020-05-28
Qubit Tuning By Magnetic Fields In Superconductors App 20200167683 - Frisch; Albert ; et al.	2020-05-28
Digital Logic Circuit For Deterring Race Violations At An Array Test Control Boundary Using An Inverted Array Clock Signal Featu App 20200127649 - Barowski; Harry ; et al.	2020-04-23
Testing content addressable memory and random access memory Grant 10,593,420 - Barowski , et al.	2020-03-17
Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature Grant 10,587,248 - Barowski , et al.	2020-03-10
Layout of large block synthesis blocks in integrated circuits Grant 10,534,884 - Barowski , et al. Ja	2020-01-14
Layout Of Large Block Synthesis Blocks In Integrated Circuits App 20190294739 - Barowski; Harry ; et al.	2019-09-26
Layout of large block synthesis blocks in integrated circuits Grant 10,417,366 - Barowski , et al. Sept	2019-09-17
Layout of large block synthesis blocks in integrated circuits Grant 10,366,191 - Barowski , et al. July 30, 2	2019-07-30
Digital logic circuit for deterring race violations at an array test control boundary using an inverted array clock signal feature Grant 10,367,481 - Barowski , et al. July 30, 2	2019-07-30
Integrated Circuit Design Changes Using Through-silicon Vias App 20190220570 - Barowski; Harry ; et al.	2019-07-18
Cross bar switch structure for highly congested environments Grant 10,333,508 - Barowski , et al.	2019-06-25
Layout of large block synthesis blocks in integrated circuits Grant 10,242,140 - Barowski , et al.	2019-03-26
Layout of large block synthesis blocks in integrated circuits Grant 10,235,487 - Barowski , et al.	2019-03-19
Placement clustering-based white space reservation Grant 10,223,489 - Barowski , et al.	2019-03-05
Integrated circuit design changes using through-silicon vias Grant 10,223,491 - Barowski , et al.	2019-03-05
Layout Of Large Block Synthesis Blocks In Integrated Circuits App 20190065636 - Barowski; Harry ; et al.	2019-02-28
Layout Of Large Block Synthesis Blocks In Integrated Circuits App 20190065635 - Barowski; Harry ; et al.	2019-02-28
Testing content addressable memory and random access memory Grant 10,170,199 - Barowski , et al. J	2019-01-01
Area sharing between multiple large block synthesis (LBS) blocks Grant 10,169,519 - Barowski , et al. J	2019-01-01
Cross Bar Switch Structure For Highly Congested Environments App 20180287598 - BAROWSKI; Harry ; et al.	2018-10-04
Testing content addressable memory and random access memory Grant 10,079,070 - Barowski , et al. September 18, 2	2018-09-18
Digital Logic Circuit App 20180212594 - Barowski; Harry ; et al.	2018-07-26
Digital Logic Circuit App 20180212595 - Barowski; Harry ; et al.	2018-07-26
Area Sharing Between Multiple Large Block Synthesis (lbs) Blocks App 20180189439 - Barowski; Harry ; et al.	2018-07-05
Testing Content Addressable Memory And Random Access Memory App 20180174666 - Barowski; Harry ; et al.	2018-06-21
Testing Content Addressable Memory And Random Access Memory App 20180151248 - Barowski; Harry ; et al.	2018-05-31
Placement Clustering-based White Space Reservation App 20180150584 - Barowski; Harry ; et al.	2018-05-31
Testing Content Addressable Memory And Random Access Memory App 20180114585 - Barowski; Harry ; et al.	2018-04-26
Area sharing between multiple large block synthesis (LBS) blocks Grant 9,946,830 - Barowski , et al. April 17, 2	2018-04-17
Layout Of Large Block Synthesis Blocks In Integrated Circuits App 20180101625 - Barowski; Harry ; et al.	2018-04-12
Layout Of Large Block Synthesis Blocks In Integrated Circuits App 20180101626 - Barowski; Harry ; et al.	2018-04-12
Layout of large block synthesis blocks in integrated circuits Grant 9,928,329 - Barowski , et al. March 27, 2	2018-03-27
Layout of large block synthesis blocks in integrated circuits Grant 9,910,948 - Barowski , et al. March 6, 2	2018-03-06
Area Sharing Between Multiple Large Block Synthesis (lbs) Blocks App 20170351798 - Barowski; Harry ; et al.	2017-12-07
Pipelining out-of-order instructions Grant 9,733,945 - Barowski , et al. August 15, 2	2017-08-15
Layout Of Large Block Synthesis Blocks In Integrated Circuits App 20170212970 - Barowski; Harry ; et al.	2017-07-27
Layout Of Large Block Synthesis Blocks In Integrated Circuits App 20170212969 - Barowski; Harry ; et al.	2017-07-27
De-coupling capacitance placement Grant 9,684,759 - Barowski , et al. June 20, 2	2017-06-20
De-coupling capacitance placement Grant 9,679,099 - Barowski , et al. June 13, 2	2017-06-13
Integrated Circuit Design Changes Using Through-silicon Vias App 20170154148 - Barowski; Harry ; et al.	2017-06-01
Techniques for increasing instruction issue rate and reducing latency in an out-of order processor Grant 9,658,853 - Barowski , et al. May 23, 2	2017-05-23
Through-silicon via access device for integrated circuits Grant 9,633,928 - Barowski , et al. April 25, 2	2017-04-25
Integrated circuit design changes using through-silicon vias Grant 9,569,580 - Barowski , et al. February 14, 2	2017-02-14
De-coupling Capacitance Placement App 20170004248 - Barowski; Harry ; et al.	2017-01-05
De-coupling Capacitance Placement App 20170004239 - Barowski; Harry ; et al.	2017-01-05
Integrated circuit design changes using through-silicon vias Grant 9,501,603 - Barowski , et al. November 22, 2	2016-11-22
Write address synchronization in 2 read/1write SRAM arrays Grant 9,437,285 - Barowski , et al. September 6, 2	2016-09-06
Write address synchronization in 2 read/1write SRAM arrays Grant 9,406,375 - Barowski , et al. August 2, 2	2016-08-02
Pipelining out-of-order instructions Grant 9,395,996 - Barowski , et al. July 19, 2	2016-07-19
Pipelining Out-of-order Instructions App 20160179551 - Barowski; Harry ; et al.	2016-06-23
Transferring heat through an optical layer of integrated circuitry Grant 9,337,122 - Barowski , et al. May 10, 2	2016-05-10
Through-silicon Via Access Device For Integrated Circuits App 20160071783 - Barowski; Harry ; et al.	2016-03-10
Integrated Circuit Design Changes Using Through-silicon Vias App 20160070840 - Barowski; Harry ; et al.	2016-03-10
Through-silicon Via Access Device For Integrated Circuits App 20160071786 - Barowski; Harry ; et al.	2016-03-10
Integrated Circuit Design Changes Using Through-silicon Vias App 20160070842 - Barowski; Harry ; et al.	2016-03-10
Three-dimensional permute unit for a single-instruction multiple-data processor Grant 9,268,738 - Barowski , et al. February 23, 2	2016-02-23
Transferring Heat Through An Optical Layer Of Integrated Circuitry App 20150221575 - Barowski; Harry ; et al.	2015-08-06
Transferring heat through an optical layer of integrated circuitry Grant 9,064,080 - Barowski , et al. June 23, 2	2015-06-23
Transferring heat through an optical layer of integrated circuitry Grant 9,058,461 - Barowski , et al. June 16, 2	2015-06-16
Integrated circuit package connected to an optical data transmission medium using a coolant Grant 8,989,532 - Barowski , et al. March 24, 2	2015-03-24
Charge recycling between power domains of integrated circuits Grant 8,984,314 - Barowski , et al. March 17, 2	2015-03-17
Charge recycling between power domains of integrated circuits Grant 8,972,758 - Barowski , et al. March 3, 2	2015-03-03
Techniques For Increasing Instruction Issue Rate And Reducing Latency In An Out-of-order Processor App 20150039862 - BAROWSKI; HARRY ; et al.	2015-02-05
Power down of execution units for issued instruction accumulation when issue rate of instructions falls below threshold and at least two are independent Grant 8,806,253 - Niggemeier , et al. August 12, 2	2014-08-12
Integrated circuit package connected to a data transmission medium Grant 8,805,132 - Barowski , et al. August 12, 2	2014-08-12
Transferring Heat Through An Optical Layer Of Integrated Circuitry App 20140095121 - Barowski; Harry ; et al.	2014-04-03
Charge Recycling Between Power Domains of Integrated Circuits App 20140082386 - Barowski; Harry ; et al.	2014-03-20
Pipelining Out-of-order Instructions App 20130346729 - Barowski; Harry ; et al.	2013-12-26
Three-Dimensional Permute Unit for a Single-Instruction Multiple-Data Processor App 20130227249 - Barowski; Harry ; et al.	2013-08-29
Optimized semiconductor packaging in a three-dimensional stack Grant 8,476,112 - Barowski , et al. July 2, 2	2013-07-02
Charge Recycling Between Power Domains of Integrated Circuits App 20130138978 - Barowski; Harry ; et al.	2013-05-30
Thermal power plane for integrated circuits Grant 8,427,833 - Barowski , et al. April 23, 2	2013-04-23
Heat sink integrated power delivery and distribution for integrated circuits Grant 8,405,998 - Barowski , et al. March 26, 2	2013-03-26
Soft-bounded hierarchical synthesis Grant 8,375,345 - Barowski , et al. February 12, 2	2013-02-12
Method And Apparatus For Improved Power Management Of Microprocessors By Instruction Grouping App 20120303991 - Niggemeier; Tim ; et al.	2012-11-29
Multistage, hybrid synthesis processing facilitating integrated circuit layout Grant 8,316,335 - Barowski , et al. November 20, 2	2012-11-20
Optimized Semiconductor Packaging in a Three-Dimensional Stack App 20120290999 - Barowski; Harry ; et al.	2012-11-15
Optimized semiconductor packaging in a three-dimensional stack Grant 8,253,234 - Barowski , et al. August 28, 2	2012-08-28
Power gating processor execution units when number of instructions issued per cycle falls below threshold and are independent until instruction queue is full Grant 8,245,065 - Niggemeier , et al. August 14, 2	2012-08-14
Transferring Heat Through An Optical Layer Of Integrated Circuitry App 20120189243 - Barowski; Harry ; et al.	2012-07-26
Integrated Circuit Package Connected To A Data Transmission Medium App 20120148187 - Barowski; Harry ; et al.	2012-06-14
Integrated Circuit Package Connected To An Optical Data Transmission Medium Using A Coolant App 20120147559 - Barowski; Harry ; et al.	2012-06-14
Multistage, Hybrid Synthesis Processing Facilitating Integrated Circuit Layout App 20120151429 - BAROWSKI; Harry ; et al.	2012-06-14
Thermal Power Plane for Integrated Circuits App 20120105145 - Barowski; Harry ; et al.	2012-05-03
Heat Sink Integrated Power Delivery and Distribution for Integrated Circuits App 20120106074 - Barowski; Harry ; et al.	2012-05-03
Optimized Semiconductor Packaging in a Three-Dimensional Stack App 20120105144 - Barowski; Harry ; et al.	2012-05-03
Formally deriving a minimal clock-gating scheme Grant 7,849,428 - Barowski , et al. December 7, 2	2010-12-07
Method And Apparatus For Improved Power Management Of Microprocessors By Instruction Grouping App 20100228955 - Niggemeier; Tim ; et al.	2010-09-09
Multi-cycle Register File Bypass App 20090249035 - Barowski; Harry ; et al.	2009-10-01
Method and system for data dependent performance increment and power reduction Grant 7,502,918 - Barowski , et al. March 10, 2	2009-03-10
Formally deriving a minimal clock-gating scheme App 20080288901 - Barowski; Harry ; et al.	2008-11-20
Circuit Arrangement and Method to Reduce Leakage Power and to Increase the Performance of a Circuit App 20070165343 - Barowski; Harry ; et al.	2007-07-19
Method to Reduce Leakage Within a Sequential Network and Latch Circuit App 20070168792 - Barowski; Harry ; et al.	2007-07-19

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.