Patent | Date |
---|
Synchronization of clock signals generated using output dividers Grant 11,342,926 - Barnette , et al. May 24, 2 | 2022-05-24 |
Method for generation of independent clock signals from the same oscillator Grant 11,245,406 - Ranganathan , et al. February 8, 2 | 2022-02-08 |
Method For Generation Of Independent Clock Signals From The Same Oscillator App 20210409031 - Ranganathan; Harihara Subramanian ;   et al. | 2021-12-30 |
Synchronization Of Clock Signals Generated Using Output Dividers App 20210184687 - Barnette; James D. ;   et al. | 2021-06-17 |
Spur and quantization noise cancellation for PLLS with non-linear phase detection Grant 11,038,521 - Rafi , et al. June 15, 2 | 2021-06-15 |
Synchronization of clock signals generated using output dividers Grant 10,951,216 - Barnette , et al. March 16, 2 | 2021-03-16 |
Using Time-to-digital Converters To Delay Signals With High Accuracy And Large Range App 20200379412 - Balakrishnan; Krishnan ;   et al. | 2020-12-03 |
Fractional Divider With Error Correction App 20200358449 - Gong; Xue-Mei ;   et al. | 2020-11-12 |
Fractional divider with error correction Grant 10,826,507 - Gong , et al. November 3, 2 | 2020-11-03 |
Accurate and reliable digital PLL lock indicator Grant 10,819,354 - Jayakumar , et al. October 27, 2 | 2020-10-27 |
Use of a virtual clock in a PLL to maintain a closed loop system Grant 10,727,845 - Balakrishnan , et al. | 2020-07-28 |
Reference clock frequency change handling in a phase-locked loop Grant 10,727,844 - Gong , et al. | 2020-07-28 |
Method for switching master/slave timing in a 1000Base-T link without traffic disruption Grant RE48,130 - Barnette , et al. | 2020-07-28 |
Gradual frequency transition with a frequency step Grant 10,693,475 - Gong , et al. | 2020-06-23 |
Accurate And Reliable Digital Pll Lock Indicator App 20200162081 - Jayakumar; Kannanthodath V. ;   et al. | 2020-05-21 |
Locking a PLL to the nearest edge of the input clock when the input clock is divided down before use in the PLL Grant 10,651,862 - Barnette , et al. | 2020-05-12 |
Method for switching master/slave timing in a 1000BASE-T link without traffic disruption Grant 8,923,341 - Barnette , et al. December 30, 2 | 2014-12-30 |
Method for switching master/slave timing in a 1000BASE-T link without traffic disruption Grant 08923341 - | 2014-12-30 |
System And Method For Squelching A Recovered Clock In An Ethernet Network App 20120224493 - Rock; Jason C. ;   et al. | 2012-09-06 |
System and method for squelching a recovered clock in an ethernet network Grant 8,179,901 - Rock , et al. May 15, 2 | 2012-05-15 |
Method For Switching Master/slave Timing In A 1000base-t Link Without Traffic Disruption App 20110170645 - Barnette; James D. ;   et al. | 2011-07-14 |
System And Method For Squelching A Recovered Clock In An Ethernet Network App 20090201924 - Rock; Jason C. ;   et al. | 2009-08-13 |
System And Method For Detecting Early Link Failure In An Ethernet Network App 20090201821 - Barnette; James D. ;   et al. | 2009-08-13 |
Resampler for a bit pump and method of resampling a signal associated therewith Grant 7,542,536 - Barnette , et al. June 2, 2 | 2009-06-02 |
Resampler for a bit pump and method of resampling a signal associated therewith App 20060023821 - Barnette; James D. ;   et al. | 2006-02-02 |
Resampler for a bit pump and method of resampling a signal associated therewith Grant 6,973,146 - Barnette , et al. December 6, 2 | 2005-12-06 |
Interpolator, a resampler employing the interpolator and method of interpolating a signal associated therewith Grant 6,970,511 - Barnette November 29, 2 | 2005-11-29 |
Circuits, system, and methods for processing multiple data streams Grant 6,055,619 - North , et al. April 25, 2 | 2000-04-25 |