loadpatents
name:-0.010231971740723
name:-0.011715888977051
name:-0.0033841133117676
Barber; Ivor G. Patent Filings

Barber; Ivor G.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Barber; Ivor G..The latest application filed is for "methods and apparatus for thermal interface material (tim) bond line thickness (blt) reduction and tim adhesion enhancement for efficient thermal management".

Company Profile
3.10.7
  • Barber; Ivor G. - Los Gatos CA
  • Barber; Ivor G. - Milpitas CA
  • Barber; Ivor G. - San Jose CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Testing system for lid-less integrated circuit packages
Grant 10,527,670 - Refai-Ahmed , et al. J
2020-01-07
Methods and apparatus for thermal interface material (TIM) bond line thickness (BLT) reduction and TIM adhesion enhancement for efficient thermal management
Grant 10,529,645 - Gandhi , et al. J
2020-01-07
Chip package assembly with enhanced interconnects and method for fabricating the same
Grant 10,319,606 - Gandhi , et al.
2019-06-11
Methods And Apparatus For Thermal Interface Material (tim) Bond Line Thickness (blt) Reduction And Tim Adhesion Enhancement For Efficient Thermal Management
App 20180358280 - Gandhi; Jaspreet Singh ;   et al.
2018-12-13
Method and apparatus for assembling and testing a multi-integrated circuit package
Grant 10,096,502 - Refai-Ahmed , et al. October 9, 2
2018-10-09
Testing System For Lid-less Integrated Circuit Packages
App 20180284187 - Refai-Ahmed; Gamal ;   et al.
2018-10-04
Stacked silicon package assembly having an enhanced lid
Grant 10,043,730 - Refai-Ahmed , et al. August 7, 2
2018-08-07
Method And Apparatus For Assembling And Testing A Multi-integrated Circuit Package
App 20180144963 - Refai-Ahmed; Gamal ;   et al.
2018-05-24
Stacked Silicon Package Assembly Having An Enhanced Lid
App 20170092619 - Refai-Ahmed; Gamal ;   et al.
2017-03-30
Multi-die Semiconductor Package And Method Of Manufacturing Thereof
App 20140191403 - Barber; Ivor G.
2014-07-10
Integrated Circuit System Monitor
App 20090285261 - Casey; Michael J. ;   et al.
2009-11-19
Via construction for structural support
Grant 6,943,446 - McCormick , et al. September 13, 2
2005-09-13
Via construction
App 20040089953 - McCormick, John P. ;   et al.
2004-05-13
Thermal and mechanical attachment of a heatspreader to a flip-chip integrated circuit structure using underfill
Grant 6,673,708 - Barber , et al. January 6, 2
2004-01-06
Method of packaging integrated circuits
Grant 5,801,072 - Barber September 1, 1
1998-09-01
Method of flip chip assembly
Grant 5,723,369 - Barber March 3, 1
1998-03-03
Method of packaging an integrated circuit
Grant 5,700,723 - Barber December 23, 1
1997-12-23

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