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name:-0.035913944244385
name:-0.021797895431519
Baraskar; Ashish Patent Filings

Baraskar; Ashish

Patent Applications and Registrations

Patent applications and USPTO patent grants for Baraskar; Ashish.The latest application filed is for "three-dimensional memory device with high mobility channels and nickel aluminum silicide or germanide drain contacts and method of making the same".

Company Profile
19.29.27
  • Baraskar; Ashish - Santa Clara CA
  • Baraskar; Ashish - Milpitas CA
  • Baraskar; Ashish - Clifton Park NY
  • Baraskar; Ashish - White Plains NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Methods for reusing substrates during manufacture of a bonded assembly including a logic die and a memory die
Grant 11,398,451 - Baraskar , et al. July 26, 2
2022-07-26
Three-dimensional memory device containing III-V compound semiconductor channel and contacts and method of making the same
Grant 11,374,020 - Baraskar , et al. June 28, 2
2022-06-28
Three-dimensional memory device including a silicon-germanium source contact layer and method of making the same
Grant 11,322,509 - Baraskar , et al. May 3, 2
2022-05-03
Three-dimensional memory device containing III-V compound semiconductor channel and contacts and method of making the same
Grant 11,282,857 - Baraskar , et al. March 22, 2
2022-03-22
Three-dimensional Memory Device With High Mobility Channels And Nickel Aluminum Silicide Or Germanide Drain Contacts And Method Of Making The Same
App 20220045087 - BARASKAR; Ashish ;   et al.
2022-02-10
Three-dimensional Memory Device With High Mobility Channels And Nickel Aluminum Silicide Or Germanide Drain Contacts And Method Of Making The Same
App 20220045088 - BARASKAR; Ashish ;   et al.
2022-02-10
Modified verify scheme for programming a memory apparatus
Grant 11,244,734 - Baraskar , et al. February 8, 2
2022-02-08
Three-dimensional Memory Device Containing Iii-v Compound Semiconductor Channel And Contacts And Method Of Making The Same
App 20210375908 - BARASKAR; Ashish ;   et al.
2021-12-02
Three-dimensional Memory Device Containing Iii-v Compound Semiconductor Channel And Contacts And Method Of Making The Same
App 20210375909 - BARASKAR; Ashish ;   et al.
2021-12-02
Three-dimensional Memory Device Containing Iii-v Compound Semiconductor Channel And Contacts And Method Of Making The Same
App 20210375910 - BARASKAR; Ashish ;   et al.
2021-12-02
Three-dimensional memory device containing plural work function word lines and methods of forming the same
Grant 11,101,288 - Zhang , et al. August 24, 2
2021-08-24
Three-dimensional memory device containing plural work function word lines and methods of forming the same
Grant 11,063,063 - Zhang , et al. July 13, 2
2021-07-13
Modified Verify Scheme For Programming A Memory Apparatus
App 20210202022 - Baraskar; Ashish ;   et al.
2021-07-01
Three-dimensional Memory Device Containing Plural Work Function Word Lines And Methods Of Forming The Same
App 20210183883 - ZHANG; Yanli ;   et al.
2021-06-17
Three-dimensional Memory Device Containing Plural Work Function Word Lines And Methods Of Forming The Same
App 20210183882 - ZHANG; Yanli ;   et al.
2021-06-17
Multi-pass programming process for memory device which omits verify test in first program pass
Grant 11,037,640 - Baraskar , et al. June 15, 2
2021-06-15
Memory device with compensation for program speed variations due to block oxide thinning
Grant 11,024,387 - Lu , et al. June 1, 2
2021-06-01
Reprogramming memory cells to tighten threshold voltage distributions and improve data retention
Grant 10,964,402 - Chen , et al. March 30, 2
2021-03-30
Methods For Reusing Substrates During Manufacture Of A Bonded Assembly Including A Logic Die And A Memory Die
App 20210082865 - BARASKAR; Ashish ;   et al.
2021-03-18
Memory Device With Compensation For Program Speed Variations Due To Block Oxide Thinning
App 20210082515 - Lu; Ching-Huang ;   et al.
2021-03-18
Memory device with compensation for erase speed variations due to blocking oxide layer thinning
Grant 10,923,197 - Lu , et al. February 16, 2
2021-02-16
Memory device with compensation for program speed variations due to block oxide thinning
Grant 10,878,914 - Lu , et al. December 29, 2
2020-12-29
Three-dimensional Memory Device Including A Silicon-germanium Source Contact Layer And Method Of Making The Same
App 20200388626 - BARASKAR; Ashish ;   et al.
2020-12-10
Three-dimensional Memory Device Including A Silicon-germanium Source Contact Layer And Method Of Making The Same
App 20200388688 - BARASKAR; Ashish ;   et al.
2020-12-10
Memory Device With Compensation For Erase Speed Variations Due To Blocking Oxide Layer Thinning
App 20200335168 - Lu; Ching-Huang ;   et al.
2020-10-22
Multi-pass programming process for memory device which omits verify test in first program pass
Grant 10,811,109 - Baraskar , et al. October 20, 2
2020-10-20
Three-dimensional memory devices using carbon-doped aluminum oxide backside blocking dielectric layer for etch resistivity enhancement and methods of making the same
Grant 10,804,282 - Baraskar , et al. October 13, 2
2020-10-13
Multi-pass Programming Process For Memory Device Which Omits Verify Test In First Program Pass
App 20200312414 - Baraskar; Ashish ;   et al.
2020-10-01
Memory Device With Compensation For Erase Speed Variations Due To Blocking Oxide Layer Thinning
App 20200265897 - Lu; Ching-Huang ;   et al.
2020-08-20
Three-dimensional Memory Devices Using Carbon-doped Aluminum Oxide Backside Blocking Dielectric Layer For Etch Resistivity Enhan
App 20200258896 - A1
2020-08-13
Memory device with compensation for erase speed variations due to blocking oxide layer thinning
Grant 10,741,253 - Lu , et al. A
2020-08-11
Memory Device With Compensation For Program Speed Variations Due To Block Oxide Thinning
App 20200243141 - Lu; Ching-Huang ;   et al.
2020-07-30
Multi-pass Programming Process For Memory Device Which Omits Verify Test In First Program Pass
App 20200211663 - Baraskar; Ashish ;   et al.
2020-07-02
Memory device with compensation for program speed variations due to block oxide thinning
Grant 10,665,301 - Lu , et al.
2020-05-26
Non-volatile memory with reduced program speed variation
Grant 10,497,711 - Baraskar , et al. De
2019-12-03
Semiconductor fuses with nanowire fuse links and fabrication methods thereof
Grant 10,332,834 - Wong , et al.
2019-06-25
Reducing charge loss in data memory cell adjacent to dummy memory cell
Grant 10,121,552 - Baraskar , et al. November 6, 2
2018-11-06
Three-dimensional memory device containing structurally reinforced pedestal channel portions and method of making thereof
Grant 10,115,730 - Baraskar , et al. October 30, 2
2018-10-30
Reducing Charge Loss In Data Memory Cell Adjacent To Dummy Memory Cell
App 20180308556 - Baraskar; Ashish ;   et al.
2018-10-25
Channel pre-charge to suppress disturb of select gate transistors during erase in memory
Grant 10,068,651 - Diep , et al. September 4, 2
2018-09-04
Forming memory cell film in stack opening
Grant 10,020,314 - Baraskar , et al. July 10, 2
2018-07-10
Non-volatile Memory With Reduced Variations In Gate Resistance
App 20180175054 - Baraskar; Ashish ;   et al.
2018-06-21
Non-volatile Memory With Reduced Program Speed Variation
App 20180122814 - Baraskar; Ashish ;   et al.
2018-05-03
Non-volatile Memory With Reduced Variations In Gate Resistance
App 20180033798 - Baraskar; Ashish ;   et al.
2018-02-01
Non-Volatile Memory With Reduced Program Speed Variation
App 20180033794 - Baraskar; Ashish ;   et al.
2018-02-01
Memory hole size variation in a 3D stacked memory
Grant 9,812,462 - Pang , et al. November 7, 2
2017-11-07
Method of fabricating 3D NAND
Grant 9,779,948 - Baraskar , et al. October 3, 2
2017-10-03
Three-dimensional memory device with select transistor having charge trapping gate dielectric layer and methods of making and operating thereof
Grant 9,748,266 - Baraskar , et al. August 29, 2
2017-08-29
Method of forming memory cell film
Grant 9,673,216 - Baraskar , et al. June 6, 2
2017-06-06
Semiconductor Fuses With Nanowire Fuse Links And Fabrication Methods Thereof
App 20170141031 - WONG; Chun Yu ;   et al.
2017-05-18
Semiconductor fuses with nanowire fuse links and fabrication methods thereof
Grant 9,601,428 - Wong , et al. March 21, 2
2017-03-21
Methods of fabricating nanowire structures
Grant 9,508,795 - Wong , et al. November 29, 2
2016-11-29
Semiconductor Fuses With Nanowire Fuse Links And Fabrication Methods Thereof
App 20160284643 - WONG; Chun Yu ;   et al.
2016-09-29
Methods Of Fabricating Nanowire Structures
App 20160225849 - WONG; Chun Yu ;   et al.
2016-08-04
Methods of forming group III-V semiconductor materials on group IV substrates and the resulting substrate structures
Grant 9,275,861 - Yang , et al. March 1, 2
2016-03-01
Methods Of Forming Group Iii-v Semiconductor Materials On Group Iv Substrates And The Resulting Substrate Structures
App 20150001587 - Yang; Li ;   et al.
2015-01-01

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